Freescale Semiconductor e200z3 Reference Manual page 227

Note that when a TID value in a TLB entry is all zeros, it always causes a match in the PID compare
(effectively ignoring the values of the PID register). Thus, the operating system can set the values of all
the TIDs to zero, effectively eliminating the PID value from all translation comparisons.
5.2.4 Translation Flow
The effective address, concatenated with the address space value of the corresponding MSR bit (MSR[IS]
or MSR[DS]), is compared to the appropriate number of bits of the EPN field (depending on the page size)
and the TS field of TLB entries. If the contents of the effective address plus the address space bit matches
the EPN field and TS bit of the TLB entry, that TLB entry is a candidate for a possible translation match.
In addition to a match in the EPN field and TS, a matching TLB entry must match with the current process
ID of the access (in PID0), or have a TID value of 0, indicating that the entry is globally shared among all
processes.
Figure 5-2 shows the translation match logic for the effective address plus its attributes, collectively called
the virtual address, and how it is compared with the corresponding fields in the TLB entries.
AS (from MSR[IS] or MSR[DS])
EA Page Number Bits
Figure 5-2. Virtual Address and TLB-Entry Compare Process
The page size defined for a TLB entry determines how many bits of the effective address are compared
with the corresponding EPN field in the TLB entry as shown in
bits of the real page number (RPN) field are used to form the real address.
Table 5-2. Page Size (for e200z3 Core) and EPN Field Comparison
Freescale Semiconductor
TLB_entry[V]
TLB_entry[TS]
=?
Process ID
=?
TLB_entry[TID]
=0?
TLB_entry[EPN]
=?
Page Size
SIZE Field
SIZE
(4 Kbytes)
0b0001 4 Kbytes
0b0010 16 Kbytes
0b0011 64 Kbytes
0b0100 256 Kbytes
0b0101 1 Mbyte
0b0110 4 Mbytes
e200z3 Power Architecture Core Reference Manual, Rev. 2
Private Page
Shared Page
Table 5-2. On a TLB hit, the corresponding
EA to EPN Comparison
(Bits 32–53; 2 × SIZE)
EA[32–51] = EPN[32–51]?
EA[32–49] = EPN[0–49]?
EA[32–47] = EPN[32–47]?
EA[32–45] = EPN[32–45]?
EA[32–43] = EPN[32–43]?
EA[32–41] = EPN[32–41]?
Memory Management Unit
TLB Entry Hit
5-5