Freescale Semiconductor e200z3 Reference Manual page 202

Interrupts and Exceptions
Table 4-11. Data Storage Interrupt Register Settings (continued)
Registe
r
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR Access:
Byte ordering:
External termination error (precise):
MCSR Unchanged
DEAR For access and byte-ordering exceptions, set to the effective address of a byte within the page whose access caused
the violation.
Vector IVPR[32–47] || IVOR2[48–59] || 0b0000
4.6.4 Instruction Storage Interrupt (IVOR3)
An instruction storage interrupt (ISI) occurs when no higher priority exception exists and an execute
access control exception occurs. This interrupt is implemented as defined by Book E, except for the
following:
• The byte-ordering condition does not occur in the e200z3
• The addition of precise external termination errors that occur when an instruction fetch is
terminated by assertion of a p_i_tea_b=ERROR termination response and MSR[EE]=1
• Misaligned instruction fetch exceptions
• The extension of the byte ordering exception cases.
Exception extensions implemented in e200z3 for VLE involve extending the definition of the instruction
storage interrupt to include the following:
• Byte-ordering exceptions for instruction accesses
• Misaligned instruction fetch exceptions
• Corresponding updates to the ESR as shown in
.
Interrupt Type IVOR
Instruction IVOR 3 • Access control.
storage • Precise external termination error ( p_tea_b assertion and precise recognition) and MSR[EE]=1.
• Byte ordering due to misaligned instruction across page boundary to pages with mismatched
• Misaligned Instruction fetch due to a change of flow to an odd halfword instruction boundary on
Table 4-13 lists register settings when an ISI is taken.
4-14
Setting Description
PR 0
FP 0
ME —
FE0 0
[ST], [VLEMI]. All other bits cleared.
[ST], [VLEMI], BO. All other bits cleared.
[ST], [VLEMI], XTE. All other bits cleared.
Table 4-12. ISI Exceptions and Conditions
VLE bits, or access to page with VLE set, and E indicating little-endian.
a Book E (non-VLE) instruction page, due to value in LR, CTR, or xSRR0
e200z3 Power Architecture Core Reference Manual, Rev. 2
DE
FE1 0
IS
DS
RI
Table 4-12 and Table 4-13
Causing Conditions
—
0
0
—
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