Debug Control Register 3 (Dbcr3) - Freescale Semiconductor e200z3 Reference Manual

2.12.3.4

Debug Control Register 3 (DBCR3)

DBCR3, shown in Figure
debug counter and debug counter events. For counter operation, the specific debug events that cause
counters to decrement are specified in DBCR3.
Corresponding events do not need to be (and probably should not be)
enabled in DBCR0.
The IAC1–IAC4 and DAC1–DAC2 control fields in DBCR0 are ignored for counter operations and the
control fields in DBCR3 determine when counting is enabled. DBCR1 and DBCR2 control fields are also
used to determine the configuration of IAC1–IAC4 and DAC1–DAC2 operations for counting, even
though the setting of bits in DBSR by corresponding events can be disabled via DBCR0. Multiple
count-enabled events that occur during execution of an instruction typically cause only one decrement of
a counter. For example, if more than one IAC or DAC register hits and is enabled for counting, only one
count can occur per counter. During execution of lmw and stmw instructions, multiple DACn hits can
occur. If the instruction is not interrupted before completion, a single decrement of a counter occurs.
If the counters operate independently, both may count for the same
instruction.
The debug counter register (DBCNT) is configured by DBCR3[CONFIG] to operate either as separate
16-bit counter 1 and counter 2 or as a combined 32-bit counter (using control bits in DBCR3 for counter
1). Counters are enabled when any of their respective count enable event control bits are set and either
DBCR0 or DBCR0[EDM] is set. Counter 1 can be configured to count down on a number of different
debug events. Counter 2 is also configurable to count down on instruction complete, instruction or data
address compare events, and external events.
Special capability is provided for counter 1 to be triggered to begin counting down by a subset of events
(IAC1, IAC3, DAC1R, DAC1W, DEVT1, DEVT2, and counter 2). When one or more of the counter 1
trigger bits is set (IAC1T1, IAC3T1, DAC1RT1, DAC1WT1, DEVT1T1, DEVT2T1, CNT2T1), counter
1 is frozen until at least one of the triggering events occurs and is then enabled to begin operation.
Triggering status for counter 1 is provided in the debug status register. Triggering mode is enabled by an
mtspr DBCR3 which sets one or more of the trigger enable bits and also enables counter 1. The trigger
can be re-armed by clearing the DBSR[CNT1TRG] status bit.
Most combinations of enables do not make sense and should be avoided. For example, if DBCR3[ICMP]
is set for counter 1, no other count enable should be set for counter 1. Conversely, multiple instruction
address compare count enables are allowed to be set and can be useful.
Due to instruction pipelining issues and other constraints, most combinations of events are not supported
for event counting. Only the following combinations are for use; other combinations are not supported:
• Any combination of IAC[1–4]
• Any combination of DAC[1–2] including linking
• Any combination of DEVT[1–2]
• Any combination of IRPT and RET
Freescale Semiconductor
2-36, is an e200z3 implementation-specific register to enable and configure the
NOTE
NOTE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Register Model
2-43