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Register Model
– Time base (TB). Maintains the time of day and operates interval timers. The TB consists of
two 32-bit registers, time base upper (TBU) and time base lower (TBL). Only
supervisor-level software can write to the time base registers, but both user and
supervisor-level software can read them.
– Decrementer register (DEC). A 32-bit decrementing counter for causing a decrementer
exception after a programmable delay.
– Decrementer auto-reload (DECAR). Supports the auto-reload feature of the decrementer.
– Timer control register (TCR). Controls the decrementer, fixed-interval timer, and watchdog
timer options.
– Timer status register (TSR). Contains status on timer events and the most recent
watchdog-timer-initiated processor reset.
2.2
e200z3-Specific Registers
Book E allows implementation-specific registers. Those in the e200z3 core are as follows:
•
User-level registers, which are accessible to all software with either user or supervisor privileges:
— Signal processing/embedded floating-point status and control register (SPEFSCR). Contains
all integer and floating-point exception signal bits, exception summary bits, exception enable
bits, and rounding control bits for compliance with the IEEE 754 standard.
— L1 cache configuration register (L1CFG0). A read-only register that allows software to query
the configuration of the L1 cache. For the e200z3, this register returns all zeros.
— The EIS-defined accumulator, which is part of the SPE APU. See
(ACC)."
•
Supervisor-level registers, which are defined in the e200z3 in addition to the Book E registers
described in
Section 2.1, "PowerPC Book E
— Configuration registers—Hardware implementation-dependent registers 0 and 1 (HID0 and
HID1). Control various processor and system functions.
— Exception handling and control registers:
– Machine check syndrome register (MCSR). A syndrome to differentiate between the
different kinds of conditions that can generate a machine check.
– Debug save/restore register 0 (DSRR0). When the debug APU is enabled, DSRR0 saves the
address of the instruction at which execution continues when rfdi executes at the end of a
debug interrupt handler routine.
– Debug save/restore register 1 (DSRR1). When the debug APU is enabled,
(HID0[DAPUEN] = 1), DSRR1 saves machine state from the MSR on debug interrupts and
restores machine state when rfdi executes.
— Debug facility registers
– Debug control register 3 (DBCR3). Control for debug functions not described in Book E
– Debug counter register (DBCNT). Counter capability for debug functions
— Context control registers
– Context control register (CTXCR). Control for register context selection.
2-6
e200z3 Power Architecture Core Reference Manual, Rev. 2
Section 2.7.2, "Accumulator
Registers:
Freescale Semiconductor
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