Freescale Semiconductor e200z3 Reference Manual page 102

Register Model
Bit(s) Name
22 DEVT2
23 DCNT1
24 DCNT2
25 CIRPT
26 CRET
22 BKPT
27:30 —
31 FT
2-54
Table 2-23. DBERC0 Bit Definitions (continued)
External Debug Event 2 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DBCR0[DEVT2] or
DBSR[DEVT2] fields.
1 - Event owned by software debug. DBCR0[DEVT2] and DBSR[DEVT2] are software
readable/writeable.
Debug Counter 1 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to Counter1 control and
status fields.
1 - Event owned by software debug. Counter1 control and status fields are software
readable/writeable.
Debug Counter 2 Debug Event
0 - Event owned by hardware debug.No mtspr access by software to Counter2 control and
status fields.
1 - Event owned by software debug. Counter2 control and status fields are software
readable/writeable.
Critical Interrupt Taken Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DBCR0[CIRPT] or
DBSR[CIRPT] fields.
1 - Event owned by software debug. DBCR0[CIRPT] and DBSR[CIRPT] are software
readable/writeable.
Critical Return Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DBCR0[CRET] or
DBSR[CRET] fields.
1 - Event owned by software debug. DBCR0[CRET] and DBSR[CRET] are software
readable/writeable.
Breakpoint Instruction Debug Control
0 - Breakpoint owned by hardware debug. Execution of a bkpt instruction (all 0's opcode)
results in entry into debug mode.
1 - Breakpoint owned by software debug. Execution of a bkpt instruction (all 0's opcode)
results in illegal instruction exception.
Reserved
Freeze Timer Debug Control
0 - DBCR0[FT] owned by hardware debug. No access by software.
1 - DBCR0[FT] owned by software debug. DBSR[FT] is software readable/writeable.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor