Freescale Semiconductor e200z3 Reference Manual page 369

Power architecture core
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— One watchpoint event pin, nex_evto_b
— One event in pin, nex_evti_b
— One message clock out (MCKO) pin
Registers for program trace, data trace, ownership trace, and watchpoint trigger
All features controllable and configurable through the JTAG port
Configuration of the message data out pins is controlled by the port control
register at the SoC level in multiple Nexus implementations. For single
Nexus implementations, this configuration is controlled by DC1 within the
e200z3 Nexus3 module.
In either implementation, full port mode (FPM—maximum number of
MDO pins) or reduced port mode (RPM—minimum number of MDO pins)
is supported. This setting should not be changed while the system is
running.
The configuration of the message start/end out pins, 1 or 2, is determined at
the SOC integration level. This option is hard-wired based on SOC
bandwidth requirements.
block diagram.
Freescale Semiconductor
NOTE
NOTE
Figure 10-1
e200z3 Power Architecture Core Reference Manual, Rev. 2
and
Figure 10-2
shows the functional
Nexus3/Nexus2+ Module
10-3

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