Freescale Semiconductor e200z3 Reference Manual page 115

MAS2 fields are defined in
Bits Name
32–51 EPN Effective page number.
52–57 — Reserved, should be cleared.
58 VLE VLE mode.
Identifies pages that contain instructions from the VLE APU. VLE is implemented only if the processor
supports the VLE APU. Setting both the VLE and E fields is a programming error; an attempt to fetch
instructions from a page so marked produces an ISI byte ordering exception and sets ESR[BO].
0 Instructions fetched from the page are decoded and executed as PowerPC or EIS instructions.
1 Instructions fetched from the page are decoded and executed as VLE or EIS instructions.
Implementation-dependent page attribute.
59 W Write-through required.
0 This page is a write-back with respect to the caches in the system.
1 All stores performed to this page are written through to main memory.
60 I Cache inhibited.
0 This page is cacheable.
1 This page is cache-inhibited.
61 M Memory coherence required.The e200z3 does not support the memory coherence required attribute, and
thus it is ignored.
0 Memory coherence is not required.
1 Memory coherence is required.
62 G Guarded. The e200z3ignores the guarded attribute (other than for generation of the p_hprot[4:2] attributes
on an external access), since no speculative or out-of-order processing is performed.
0 Access to this page are not guarded, and can be performed before it is known if they are required by the
sequential execution model.
1 All loads and stores to this page are performed without speculation (that is, they are known to be required).
63 E Endianness. Determines endianness for the corresponding page.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
The MAS3 register is shown in
32
Field
Reset
R/W
SPR
Freescale Semiconductor
Table 2-34.
Table 2-34. MAS2—EPN and Page Attributes
Figure 2-50.
RPN
Undefined on m_por assertion, unchanged on p_reset_b assertion
Figure 2-50. MMU Assist Register 3 (MAS3)
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
51 52 53 54 55 56 57
— U0 U1 U2 U3 UX SX UW SW UR SR
R/W
SPR 627
Register Model
Permission bits
58 59 60 61 62 63
2-67