Freescale Semiconductor e200z3 Reference Manual page 431

Pipelining. A technique that breaks operations, such as instruction processing or bus
transactions, into smaller distinct stages or tenures (respectively) so that a
subsequent operation can begin before the previous one has completed.
Precise interrupts. A category of interrupt for which the pipeline can be stopped so
instructions that preceded the faulting instruction can complete and subsequent
instructions can be flushed and redispatched after interrupt handling has
completed. See Imprecise interrupts.
Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that
identifies the type of instruction.
Program order. The order of instructions in an executing program. More specifically, this
term is used to refer to the original order in which program instructions are fetched
into the instruction queue from the cache.
Protection boundary. A boundary between protection domains.
Q
Quiesce. To come to rest. The processor is said to quiesce when an interrupt is taken or a
sync instruction is executed. The instruction stream is stopped at the decode stage
and executing instructions are allowed to complete to create a controlled context
for instructions that may be affected by out-of-order, parallel execution. See
Context synchronization.
Quiet NaN. A type of NaN that can propagate through most arithmetic operations without
signaling interrupts. A quiet NaN is used to represent the results of certain invalid
operations, such as invalid arithmetic operations on infinities or on NaNs, when
invalid. See Signaling NaN.
R
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the
condition register (CR) to reflect the result of the operation.
Referenced bit. One of two page history bits found in each page table entry. The
processor sets the referenced bit whenever the page is accessed for a read or write.
See also Page access history bits.
Register indirect addressing. A form of addressing that specifies one GPR that contains
the address for the load or store.
Register indirect with immediate index addressing. A form of addressing that specifies
an immediate value to be added to the contents of a specified GPR to form the
target address for the load or store.
Register indirect with index addressing. A form of addressing that specifies that the
contents of two GPRs be added together to yield the target address for the load or
store.
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
Glossary
Glossary-7