Freescale Semiconductor e200z3 Reference Manual page 90

Register Model
Table 2-19 describes DBCR2 fields.
Bits Name
32–33 DAC1US Data address compare 1 user/supervisor mode.
00 DAC1 debug events are not affected by MSR[PR].
01 Reserved.
10 DAC1 debug events can occur only if MSR[PR] = 0 (supervisor mode).
11 DAC1 debug events can occur only if MSR[PR] = 1 (User mode).
34–35 DAC1ER Data address compare 1 effective/real mode.
00 DAC1 debug events are based on effective address.
01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.
10 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 0.
11 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 1.
36–37 DAC2US Data Address compare 2 user/supervisor mode.
00 DAC2 debug events are not affected by MSR[PR].
01 Reserved
10 DAC2 debug events can occur only if MSR[PR] = 0 (supervisor mode).
11 DAC2 debug events can occur only if MSR[PR] = 1 (user mode).
38–39 DAC2ER Data address compare 2 effective/real mode.
00 DAC2 debug events are based on effective address.
01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.
10 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 0.
11 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 1.
40–41 DAC12M Data address compare 1/2 mode.
00 Exact address compare. DAC1 debug events can occur only if the address of the data access is equal
to the value specified in DAC1. DAC2 debug events can occur only if the address of the data access
is equal to the value specified in DAC2.
01 Address bit match. DAC1 debug events can occur only if the address of the data access ANDed with
the contents of DAC2 is equal to the contents of DAC1, also ANDed with the contents of DAC2. DAC2
debug events do not occur. DAC1US and DAC1ER settings are used.
10 Inclusive address range compare. DAC1 debug events can occur only if the address of the data
access is greater than or equal to the value specified in DAC1 and less than the value specified in
DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.
11 Exclusive address range compare. DAC1 debug events can occur only if the address of the data
access is less than the value specified in DAC1 or is greater than or equal to the value specified in
DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.
42 DAC1LNK Data address compare 1 linked.
0 No effect.
1 DAC1 debug events are linked to IAC1 debug events. IAC1 debug events do not affect DBSR.
When linked to IAC1, DAC1 debug events are conditioned based on whether the instruction also
generated an IAC1 debug event.
43 DAC2LNK Data address compare 2 linked
0 No effect.
1 DAC 2 debug events are linked to IAC3 debug events. IAC3 debug events do not affect DBSR.
When linked to IAC3, DAC2 debug events are conditioned based on whether the instruction also
generated an IAC3 debug event. DAC2 can only be linked if DAC12M specifies exact address
compare because DAC2 debug events are not generated in the other compare modes.
44–63 — Reserved for data value compare control (not supported by the e200z3).
2-42
Table 2-19. DBCR2 Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor