Freescale Semiconductor e200z3 Reference Manual page 380

Nexus3/Nexus2+ Module
Bits Name
4–3 EIC
2–0 TM
OPC and MCK_DIV must be modified only during system reset or debug
mode to ensure correct output port and output clock functionality. It is also
recommended that all other bits of DC1 be modified only in one of these two
modes.
Development control register 2 is shown in
31
Field
Reset
R/W
Number
Bits Name
31–24 EWC
23–0 —
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
10-14
Table 10-10. DC1 Field Descriptions (continued)
EVTI control
00 nex_evti_b is used for synchronization (program trace/data trace)
01 nex_evti_b is used for debug request
1X Reserved
Trace mode
000 No trace
1XX Program trace enabled
X1X Data trace enabled (not supported in Nexus2+, reserved in e200z335)
XX1 Ownership trace enabled
Figure 10-6
24 23
EWC
Figure 10-6. Development Control Register 2 (DC2)
Table 10-11. DC2 Field Descriptions
EVTO Watchpoint Configuration
00000000No watchpoints trigger nex_evto_b
1xxxxxxxWatchpoint #0 (IAC1 from Nexus1) triggers nex_evto_b
x1xxxxxxWatchpoint #1 (IAC2 from Nexus1) triggers nex_evto_b
xx1xxxxxWatchpoint #2 (IAC3 from Nexus1) triggers nex_evto_b
xxx1xxxxWatchpoint #3 (IAC4 from Nexus1) triggers nex_evto_b
xxxx1xxxWatchpoint #4 (DAC1 from Nexus1) triggers nex_evto_b
xxxxx1xxWatchpoint #5 (DAC2 from Nexus1) triggers nex_evto_b
xxxxxx1xWatchpoint #6 (DCNT1 from Nexus1) triggers nex_evto_b
xxxxxxx1Watchpoint #7 (DCNT2 from Nexus1) triggers nex_evto_b
Reserved
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
NOTE
and its fields are described in
—
All zeros
Read/Write
0x3
Description
NOTE
Table 10-11.
0
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