Freescale Semiconductor e200z3 Reference Manual page 303

memory. The slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing
and drives an OKAY response.
Another write transfer request is made during C3 to addr
because the access to addr
• Clock 4 (C4)—During C4, write data for addr
using the address and attribute values (driven during C3) to enable reading of one or more bytes of
memory. The slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing
and drives an OKAY response.
Because the CPU has no more outstanding requests, p_[d,i]_htrans indicates IDLE and the address
and attribute signals are undefined.
7.5.1.4 Write Transfer with Wait States
Figure 7-6 shows an example write wait state operation. Because p_[d,i]_hready for the first request
(addr ) is not asserted during C2, a wait state is inserted until p_[d,i]_hready is recognized (during C3).
x
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-6. Write with Wait-state, Single-Cycle Writes, Full Pipelining
Meanwhile, the core generates a subsequent request for addr
previous transaction is outstanding. The address, transfer attributes, and write data remain driven in cycle
C3 and are taken at the end of C3 because a ready/OKAY response is driven back by the slave device for
the previous access. In cycle C4, a request for addr
end of C4, and during C5, the slave device provides a ready/OKAY response. In C5, no further accesses
are requested.
Freescale Semiconductor
is completing, it is considered taken at the end of C3.
y
1 2
nonseq nonseq
addr x addr y
single single
data x
okay okay
z
e200z3 Power Architecture Core Reference Manual, Rev. 2
(p_[d,i]_htrans = NONSEQ), and
z
is driven, and the addr
z
3 4
nonseq
addr z
single
data y
okay okay
which is not taken in C2, because the
y
is made. The request for access to addr
External Core Complex Interfaces
memory access takes place
z
5 6
idle
data z
okay
is taken at the
z
7-35