Freescale Semiconductor e200z3 Reference Manual page 85

32 33 34 35
Field EDM IDM RST ICMP
Reset
R/W
48 49
RET —
Reset
R/W
SPR
1
DBCR0[EDM] is affected by j_trst_b or m_por assertion, and while in the test_logic_reset state, but not by p_reset_b .
All other bits are reset by processor reset p_reset_b as well as by m_por .
Table 2-17 provides field definitions for DBCR0.
Bits Name
32 EDM External debug mode. For software, this bit is read-only. Software can use EDM to determine whether external
debug has control over debug registers. The hardware debugger must set EDM before other DBCR0 bits (and
other debug registers) can be altered. On the initial setting of EDM, all other bits are unchanged. EDM is
writable only through the OnCE port.
0 External debug mode is disabled. Internal debug events not mapped into external debug events.
1 External debug mode is enabled. Events do not cause the CPU to vector to interrupt code. Software is not
permitted to write to debug registers (DBCR0
permitted by settings in DBERC0.
Note: DBSR status bits should be cleared before external debug mode is disabled to avoid internal imprecise
debug interrupts.
When external debug mode is enabled, hardware-owned resources in debug registers are not affected by
processor reset p_reset_b. This allows the debugger to set up hardware debug events which remain active
across a processor reset.
33 IDM Internal debug mode.
0 Debug exceptions are disabled. Debug events do not affect DBSR.
1 Debug exceptions are enabled. Enabled debug events update the DBSR. If MSR[DE] = 1, a debug event or
the recording of an earlier debug event in the DBSR when MSR[DE] was cleared causes a debug interrupt.
34–35 RST Reset control.
00 No function.
01 Reserved.
10 p_resetout_b set by debug reset control. Allows external device to initiate processor reset.
11 Reserved.
36 ICMP Instruction complete debug event enable.
0 ICMP debug events are disabled.
1 ICMP debug events are enabled.
Freescale Semiconductor
36 37 38
BRT IRPT
52 53 54
DEVT1 DEVT2 DCNT1
Figure 2-33. DBCR0 Register
Table 2-17. DBCR0 Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
39 40 41
TRAP IAC1 IAC2
1
All zeros
R/W
55 56 57
DCNT2 CIRPT
1
All zeros
R/W
SPR 308
Description
–
DBCR3, DBSR, DBCNT, IAC1
Register Model
42 43 44 45 46 47
IAC3 IAC4 DAC1 DAC2
58 59 62 63
CRET VLES — FT
–
IAC4, DAC1–DAC2) unless
2-37