Freescale Semiconductor e200z3 Reference Manual page 244

Instruction Pipeline and Execution Timing
HID0[BPRED] controls whether prediction is made for forward or backward branches (or both).
To resolve branch instructions and improve the accuracy of branch predictions, the e200z3 implements a
dynamic branch prediction mechanism using an 8-entry branch target buffer (BTB), a fully associative
address cache of branch target addresses. The BTB is purposefully small to reduce cost and power. It is
expected to accelerate the execution of loops with some potential change of flow within the loop body.
An entry is allocated in the BTB whenever a branch resolves as taken and the BTB is enabled. Branches
that have not been allocated are always predicted as not taken. BTB entries are allocated on taken branches
using a FIFO replacement algorithm.
Each BTB entry holds a 2-bit branch history counter, whose value is incremented or decremented on a
BTB hit, depending on whether the branch was taken. The counter can assume four different values:
strongly taken, weakly taken, weakly not taken, and strongly not taken.
A branch is predicted as taken on a hit in the BTB with a counter value of strongly or weakly taken. In this
case, the target address contained in the BTB is used to redirect the instruction fetch stream to the target
of the branch prior to the branch reaching the instruction decode stage. In the case of a mispredicted
branch, the instruction fetch stream returns to the sequential instruction stream after the branch has been
resolved.
When a branch is predicted taken and the branch is later resolved (in the branch decode stage), the value
of the counter is updated. A branch whose counter indicates weakly taken is resolved as taken, the counter
6-6
DATA 0:63
MUX
IR
Decode
Figure 6-3. Instruction Buffers
e200z3 Power Architecture Core Reference Manual, Rev. 2
Slot3
Slot2
Slot1
Slot0
Freescale Semiconductor