Freescale Semiconductor e200z3 Reference Manual page 300

External Core Complex Interfaces
7.5.1.1 Basic Read Transfer Cycles
During a read transfer, the core receives data from a memory or peripheral device.
functional timing for basic read transfers, and clock-by-clock descriptions of activity follow.
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-3. Basic Read Transfer—Single-Cycle Reads, Full Pipelining
• Clock 1 (C1)—The first read transfer starts in clock cycle 1. During C1, the core places valid values
on the address bus and transfer attributes. The burst type (p_[d,i]_hburst[2:0]), protection control
(p_[d,i]_hprot[5:0]), and transfer type (p_[d,i]_htrans[1:0]) attributes identify the specific access
type. The transfer size attributes (p_[d,i]_hsize[1:0]) indicate the size of the transfer. The byte
strobes (p_[d,i]_hbstrb[7:0]) are driven to indicate active byte lanes. The write (p_[d,i]_hwrite)
signal is driven low for a read cycle.
The core asserts a transfer request (p_[d,i]_htrans= NONSEQ) during C1 to indicate that a transfer
is being requested. Because the bus is currently idle, (0 transfers outstanding), the first read request
to addr is considered taken at the end of C1. The default slave drives a ready/OKAY response for
x
the current idle cycle.
• Clock 2 (C2)—During C2, the addr
values that were driven during C1 to enable reading of 1 or more bytes of memory. Read data from
the slave device is provided on the p_[d,i]_hrdata inputs. The slave device responds by asserting
p_[d,i]_hready to indicate that the cycle is completing, and it drives an OKAY response.
Another read transfer request is made during C2 to addr
because the access to addr
• Clock 3 (C3)—During C3, the addr
values that were driven during C2 to enable reading of one or more bytes of memory. Read data
7-32
1 2
nonseq nonseq
addr x addr y
single single
data x
okay
memory access takes place, using the address and attribute
x
is completing, it is considered taken at the end of C2.
x
memory access takes place, using the address and attribute
y
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq
addr z
single
data y
okay okay
(p_[d,i]_htrans = NONSEQ), and
y
Figure 7-3 shows
4 5
idle
data z
okay
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