Freescale Semiconductor e200z3 Reference Manual page 214

Interrupts and Exceptions
Bits Name
34–35 WRS 00 No action performed by watchdog timer
01 Watchdog timer second timeout caused checkstop.
10 Watchdog timer second timeout caused p_resetout_b to be asserted.
11 Reserved
Table 4-27 shows the DBSR bits associated with reset status.
Bits Name
34–35 MRR 00 No reset occurred since these bits were last cleared by software.
01 A reset occurred since these bits were last cleared by software.
1 x Reserved
Table 4-28 lists register settings when a system reset is taken.
Register
CSRR0 Undefined
CSRR1 Undefined
MSR UCLE 0
WE 0
CE 0
ESR Cleared
DEAR Undefined
Vector [ p_rstbase[0:19] ] || 0xFFC in e200z3
[ p_rstbase[0:29] ] || 2'b00 in e200z335
4.6.18 SPE APU Unavailable Interrupt (IVOR32)
The SPE APU unavailable exception is taken if MSR[SPE] is cleared and execution of an SPE APU
instruction other than an embedded scalar floating-point or brinc instruction is attempted. When the SPE
APU unavailable exception occurs, the processor suppresses execution of the instruction causing the
exception. Table 4-29 lists register settings when an SPE unavailable interrupt is taken.
Register
SRR0 Set to the effective address of the excepting SPE instruction
SRR1 Set to the contents of the MSR at the time of the interrupt
4-26
Table 4-26. TSR Watchdog Timer Reset Status
Table 4-27. DBSR Most Recent Reset
Table 4-28. System Reset Register Settings
Setting Description
EE 0
PR 0
FP 0
ME 0
Table 4-29. SPE Unavailable Interrupt Register Settings
Setting Description
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Function
DE 0
FE1 0
IS 0
DS 0
RI 0
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