Freescale Semiconductor e200z3 Reference Manual page 211

Exception
Instruction Instruction address compare events are enabled and an instruction address match occurs as defined by the
address debug control registers. This could either be a direct instruction address match or a selected set of instruction
compare (IAC) addresses. IAC has the highest priority of all instruction-based interrupts, even if the instruction itself
encountered an ITLB error or instruction storage exception.
Return (RET) Return exceptions are enabled and rfi is executed. Return debug exceptions are not generated for rfci or rfdi.
If MSR[DE] = 1 when rfi executes, a debug interrupt occurs if no higher priority, enabled exception exists.
CSRR0 (debug APU disabled) or DSRR0 (debug APU enabled) is to set the address of the rfi. If MSR[DE] = 0
when rfi executes, a debug interrupt does not occur immediately; the event is recorded by setting DBSR[RET]
and DBSR[IDE].
Critical return Critical return debug events are enabled and rfci is executed. Critical return debug exceptions are only
(CRET) generated for rfci. If MSR[DE]=1 when rfci executes, a debug interrupt occurs if no higher priority exception
exists that is enabled to cause an interrupt. CSRR0 (debug APU disabled) or DSRR0 (debug APU enabled) is
set to the address of the rfci. If MSR[DE] = 0 when rfci executes, a debug interrupt does not occur immediately,
but the event is recorded by setting DBSR[CRET] and DBSR[IDE]. Note that critical return debug events should
not normally be enabled unless the debug APU is enabled to avoid corrupting CSRR0 and CSRR1.
Instruction An instruction completed while this event is enabled. A mtmsr or mtdbcr0 that causes both MSR[DE] and
complete DBCR0[IDM] to end up set, enabling precise debug mode, may cause an imprecise (delayed) debug exception
(ICMP) to be generated due to an earlier recorded event in the DBSR.
Interrupt taken A non-critical interrupt context switch is detected. This exception is imprecise and unordered with respect to
(IRPT) the program flow. Note that an IRPT debug interrupt occurs only when detecting a non-critical interrupt on the
e200z3. The value saved in CSRR0/DSRR0 is the address of the non-critical interrupt handler.
Critical A critical interrupt context switch is detected. This exception is imprecise and unordered with respect to
interrupt taken program flow. Note that a CIRPT debug interrupt occurs only when detecting a critical interrupt on the e200z3.
(CIRPT) The address of the critical interrupt handler is saved in CSRR0/DSRR0. To avoid corrupting CSRR0 and
CSRR1, critical interrupt taken debug events should not normally be enabled unless the debug APU is enabled.
Unconditional The unconditional debug event signal ( p_ude ) transitions to asserted state.
debug event
(UDE)
Debug counter A debug counter exception is enabled and a debug counter decrements to zero.
External An external debug exception is enabled and an external debug event ( p_devt1 , p_devt2 ) transitions to the
debug asserted state.
The DBSR provides a syndrome to differentiate among debug exceptions that can generate the same
interrupt. Table 4-25 lists register settings when a debug interrupt is taken.
Register
CSRR0 (MSR[DE]=0) Set to the effective address of the excepting instruction for IAC, BRT, RET, CRET, and TRAP.
1
DSRR0 Set to the effective address of the next instruction to be executed following the excepting instruction for
(MSR[DE]=1) DAC and ICMP.
For UDE, IRPT, CIRPT, DCNT, or DEVT type exceptions, set to the effective address of the instruction
that would have attempted to execute next if no exception conditions were present.
CSRR1/ DSRR1 Set to the contents of the MSR at the time of the interrupt
Freescale Semiconductor
Table 4-24. Debug Exceptions (continued)
Table 4-25. Debug Interrupt Register Settings
e200z3 Power Architecture Core Reference Manual, Rev. 2
Cause
Setting Description
Interrupts and Exceptions
4-23