Freescale Semiconductor e200z3 Reference Manual page 364

Debug Support
To ensure FIFO coherence, a complete set of eight reads of the FIFO should be performed because each
read increments the temporary FIFO pointer, thus making it point to the next location. After eight reads
the pointer points to the same location it pointed to before starting the read procedure. The temporary
counter value captures the actual counter each time the OCMD RS field transitions to the value
corresponding to the PC FIFO (010 1101).
The FIFO pointer is reset to entry 0 when either j_trst_b or m_por is set.
9.5.10 Reserved Registers
The reserved registers are used to control various test control logic. These registers are not intended for
customer use. To preclude device and/or system damage, these registers should not be accessed.
9.6 Watchpoint Support
The core supports the generation and signaling of watchpoints when operating in internal debug mode
(DBCR0[IDM] = 1) or in external debug mode (DBCR0[EDM] = 1). Watchpoints are indicated with a
dedicated set of interface signals. The jd_watchpoint[0:7] output signals are used to indicate that a
watchpoint has occurred.
Each debug address compare function (IAC1–IAC4, DAC1 and DAC2) and debug counter event (DCNT1
and DCNT2) can trigger a watchpoint output. The DBCR1, DBCR2, and DBCR3 control fields are used
to configure watchpoints, regardless of whether events are enabled in DBCR0. Watchpoints may occur
whenever an associated event would have been posted in the debug status register if enabled. No explicit
enable bits are provided for watchpoints; they are always enabled by definition (except during a debug
session). If not desired, the base address values for these events may be programmed to an unused system
address. MSR[DE] has no effect on watchpoint generation.
External logic may monitor the assertion of these signals for debugging purposes. Watchpoints are
signaled in the clock cycle following the occurrence of the actual event. The Nexus3 or Nexus 2+ module
also monitors assertion of these signals for various development control purposes (see
"Watchpoint Support").
Signal Name Type
jd_watchpt[0] IAC1 Instruction address compare 1 watchpoint. Set whenever an IAC1 compare occurs regardless of
whether IAC1 compares are enabled to set DBSR status.
jd_watchpt[1]
IAC2 Instruction address compare 2 watchpoint. Set whenever an IAC2 compare occurs regardless of
whether IAC2 compares are enabled to set DBSR status.
jd_watchpt[2]
IAC3 Instruction address compare 3 watchpoint. Set whenever an IAC3 compare occurs regardless of
whether IAC3 compares are enabled to set DBSR status.
jd_watchpt[3]
IAC4 Instruction address compare 4 watchpoint. Set whenever an IAC4 compare occurs regardless of
whether IAC4 compares are enabled to set DBSR status.
1
jd_watchpt[4] DAC1 Data address compare 1 watchpoint. Set whenever a DAC1 compare occurs regardless of whether
DAC1 compares are enabled to set DBSR status.
9-32
Table 9-12. Watchpoint Output Signal Assignments
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Section 9.6,
Freescale Semiconductor