Freescale Semiconductor e200z3 Reference Manual page 34

e200z335 Core Complex Overview
Additional Features
• OnCe/Nexus 1/Nexus 3
control logic
• AMBA AHB-Lite bus
• SPE (SIMD)
• VLE
• Embedded scalar/
vector floating-point
• Power management
• Time base/ decrementer
counter
• Clock multiplier
Execute Stage
32 GPRs
Four-cycle,
(64-Bit)
single-path
execute stage
with overlapped
execution and
feed forwarding
CR
XER
LR
CTR
Write-Back Stage
SPRs
1-2
Instruction/Control Unit
Instruction Buffer
(7 instructions)
Decode
Stage
Single-instruction, in-order dispatch
Execution Units
Embedded
Scalar FPU
+ x ÷
Embedded
Vector FPU
+ x ÷
VLE
Single-Instruction, In-Order Write Back
e200z3
Figure 1-1.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Fetch Unit
Two/Four
instructions
Program Counter
Two-Cycle
Fetch Stage
Branch Processing Unit
+
EA Calc
8-Entry Branch
Target Buffer
SPE Branch
Unit Unit
+ x ÷
Address
Load/Store
Integer
Unit
Unit
+ x ÷ + EA Calc
Optional
Extension
Address
Block Diagram
Unified Memory Unit
Software-Managed
L1 Unified MMU
16-Entry
Fully Associative
•
•
•
TLB
4-, 16-, 64-, 256-Kbyte;
1-, 4-, 16-, 64-,
256-Mbyte page sizes
MAS
Registers
Instruction Bus Interface Unit
32 64
Data Control
Data Bus Interface Unit
32 64
Data Control
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