Freescale Semiconductor e200z3 Reference Manual page 339

Event Name Type
Instruction IAC
Address Compare
Event
Data Address DAC
Compare Event
Freescale Semiconductor
Table 9-2. Debug Event Descriptions
Occurs when enabled and upon attempted execution of an instruction at an address
that meets the criteria specified in the DBCR0, DBCR1,and IAC n registers. Instruction
address compares may specify user/supervisor mode and instruction space
(MSR[IS]), along with an effective address, masked effective address, or range of
effective addresses for comparison. This event can occur and be recorded in DBSR
regardless of the setting of MSR[DE]. IAC events do not occur when an instruction
would not have normally begun execution due to a higher priority exception at an
instruction boundary.
IAC compares perform a 31-bit compare for VLE instruction pages, and 30-bit
compares for BookE instruction pages. Each half-word fetched by the instruction fetch
unit will be marked with a set of bits indicating whether an Instruction Address
Compare occurred on that half-word. Debug exceptions will occur if enabled and a
16-bit instruction, or the first half-word of a 32-bit instruction, is tagged with an IAC hit.
For instruction fetches that miss in the TLB, Book E pages are assumed, and a 30-bit
compare is performed.
Data address compare debug events occur if data address compare debug events are
enabled and execution of a load or store class instruction or a cache maintenance
instruction results in a data access with an address that meets the criteria specified
in DBCR0, DBCR2, DAC1, and DAC2. Data address compares may specify
user/supervisor mode and data space (MSR[DS]), along with an effective address,
masked effective address, or range of effective addresses for comparison. This event
can occur and be recorded in DBSR regardless of the setting of MSR[DE]. Two
address compare values (DAC1 and DAC2) are provided.
Note:
In contrast to the Book E definition, data address compare events on the core do not
prevent the load or store instruction from completing. If a load or store class
instruction completes successfully without a data TLB or data storage interrupt, data
address compare exceptions are reported at the completion of the instruction. If the
exception results in a precise debug interrupt, the address value saved in DSRR0 (or
CSRR0 if the debug APU is disabled) is the address of the instruction following the
load or store class instruction.
If a load or store class instruction does not complete successfully due to a data TLB
or data storage exception, and a data address compare debug exception also occurs,
the result is an imprecise debug interrupt, the address value saved in DSRR0 (or
CSRR0 if the debug APU is disabled) is the address of the load or store class
instruction, and DBSR[IDE] is set. In addition to occurring when DBCR0[IDM] = 1, this
can also occur when DBCR0[EDM] = 1.
Note:
DAC events are not recorded or counted if an lmw or stmw instruction is interrupted
before completion by a critical input or external input interrupt.
Note:
• DAC events are not signaled on the following:
—The second portion of a misaligned load or store that is broken up into two
separate accesses
—The tlbre, tlbwe, tlbsx, or tlbivax instructions
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Debug Support
9-7