Freescale Semiconductor e200z3 Reference Manual page 18

Figure
Number
7-25 Misaligned Write with Error, Data Write Retracted, Burst Read
Substituted, Full Pipelining .............................................................................................. 7-54
7-26 Burst Read with Error Termination, Burst Write .................................................................. 7-55
7-27 Read Transfer with Wait-State, Address Retraction ............................................................. 7-56
7-28 Burst Read with Wait-State Transfer, Retraction .................................................................. 7-57
7-29 Wakeup Control Signal (p_wakeup) ..................................................................................... 7-57
7-30 Interrupt Interface Input Signals ........................................................................................... 7-58
7-31 Interrupt Pending Operation.................................................................................................. 7-58
7-32 Interrupt Acknowledge Operation Case 1............................................................................. 7-59
7-33 Interrupt Acknowledge Operation Case 2............................................................................. 7-60
8-1 Power Management State Diagram......................................................................................... 8-2
9-1 Core Debug Resources............................................................................................................ 9-3
9-2 OnCE TAP Controller and Registers .................................................................................... 9-11
9-3 OnCE Controller as an FSM ................................................................................................. 9-12
9-4 OnCE Controller and Serial Interface ................................................................................... 9-16
9-5 OnCE Status Register (OSR) ................................................................................................ 9-17
9-6 OnCE Command Register (OCMD) ..................................................................................... 9-18
9-7 OnCE Control Register ......................................................................................................... 9-20
9-8 CPU Scan Chain Register (CPUSCR) .................................................................................. 9-25
9-9 Control State Register (CTL) ................................................................................................ 9-26
9-10 OnCE PC FIFO ..................................................................................................................... 9-30
10-1 Nexus3 Functional Block Diagram....................................................................................... 10-4
10-2 Client Select Control Register............................................................................................. 10-10
10-3 Port Configuration Register ................................................................................................ 10-11
10-4 Development Control Register 1 (DC1) ............................................................................. 10-12
10-5 Development Control Register 2 (DC2) ............................................................................. 10-13
10-6 Development Status Register (DS) ..................................................................................... 10-14
10-7 Read/Write Access Control/Status Register (RWCS) ......................................................... 10-15
10-8 Read/Write Access Data Register (RWD) .......................................................................... 10-16
10-9 Read/Write Access Address Register (RWA) ..................................................................... 10-17
10-10 Watchpoint Trigger Register (WT) ..................................................................................... 10-18
10-11 Data Trace Control Register (DTC) .................................................................................... 10-19
10-12 Data Trace Start Address Registers 1 and 2 (DTSAn)........................................................ 10-20
10-13 Data Trace End Address Registers 1 and 2 (DTEAn)......................................................... 10-20
10-14 Nexus3 Register Access through JTAG/OnCE (Example) ................................................. 10-21
10-15 Ownership Trace Message Format...................................................................................... 10-23
10-16 Error Message Format......................................................................................................... 10-23
10-17 Indirect Branch Message (History) Format ........................................................................ 10-26
10-18 Indirect Branch Message Format ........................................................................................ 10-26
10-19 Direct Branch Message Format........................................................................................... 10-26
10-20 Resource Full Message Format........................................................................................... 10-27
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Figures
Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor