Freescale Semiconductor e200z3 Reference Manual page 99

Debug Status bits in DBSR are set by software-owned debug events only while Internal Debug Mode is
enabled. When debug interrupts are enabled (MSR[DE]=1 DBCR0[IDM]=1 and DBCR0[EDM]=0, or
MSR[DE]=1, DBCR0[IDM]=1 and DBCR0[EDM]=1 and software is allocated resource(s) via
DBERC0), a set bit in DBSR which is software-owned other than MRR or VLES will cause a debug
interrupt to be generated.
Debug Status bits in DBSR are set by hardware-owned debug events only while External Debug Mode is
enabled (DBCR0[EDM]=1).
If DBERC0[IDM]=1, all DBSR status bits corresponding to hardware-owned debug events are masked to
0 when accessed by software. The actual values in the DBSR register is always visible to hardware when
accessed via the OnCE port.
Software-owned resources may be modified by software, but only the corresponding control and status
bits in DBCR0-4 and DBSR are affected by execution of a mtspr, thus only a portion of these registers
may be affected, depending on the allocation settings in DBERC0. The debug interrupt handler is still
responsible for clearing software-owned DBSR bits prior to returning to normal execution. Hardware
always has full access to all registers and all register fields through the OnCE register access mechanism,
and it is up to the debug firmware to properly implement modifications to these registers with
read-modify-write operations to implement any control sharing with software. Settings in DBERC0
should be considered by the debug firmware in order to preserve software settings of control and status
registers as appropriate when hardware modifications to the debug registers is performed.
The DBERC0 register is shown in
0
0 1 2 3 4 5 6
SPR - 569; Read-only by Software; Reset - Unaffected by p_reset_b, cleared by m_por or while in the test-logic-reset
Freescale Semiconductor
Figure 2-39.
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
OnCE controller state
Figure 2-39. DBERC0 Register
e200z3 Power Architecture Core Reference Manual, Rev. 2
0 0
Register Model
2-51