Freescale Semiconductor e200z3 Reference Manual page 304

External Core Complex Interfaces
7.5.1.5 Read and Write Transfers
Figure 7-7 shows a sequence of read and write cycles.
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-7. Single-Cycle Reads, Single-Cycle Write, Full Pipelining
The first read request (addr
(addr ) is taken at the end of C2 because a ready/OKAY response is asserted during C2 for the first read
y
access (addr ). During C3, a request is generated for a write to addr
x
because the second access is terminating.
Data for the addr write cycle is driven in C4, the cycle after the access is taken, and a ready/OKAY
z
response is signaled to complete the write cycle to addr
Figure 7-8 shows another sequence of read and write cycles. This example shows an interleaved write
access between two reads.
7-36
1 2
nonseq nonseq
addr x addr y
single single
data x
okay
) is taken at the end of cycle C1 because the bus is idle. The second read request
x
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq
addr z
single
data y
okay okay
which is taken at the end of C3
y
.
z
4 5
idle
data z
okay
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