Freescale Semiconductor e200z3 Reference Manual page 352

Debug Support
Bits Name
2 EX Exit. The Exit command is executed only if the Go command is issued and the operation is a read/write to
CPUSCR or a read/write to no register selected. Otherwise, the EX bit is ignored.
The processor leaves debug mode after the TAP controller Update-DR state is entered. Note that if the DR bit in
the OnCE control register is set or remains set, or if a bit in the DBSR is set, or if a bit in the DBSR is set and
DBCR0[EDM] = 1 (external debug mode is enabled), then the processor may return to the debug mode without
execution of an instruction, even though the EX bit was set.
0 Remain in debug mode
1 Leave debug mode. The processor leaves debug mode and resumes normal operation until another debug
request is generated.
3–9 RS Register select. Defines which register is the source for the read or the destination for the write operation.
Table 9-9 indicates the OnCE register addresses. Attempted writes to read-only registers are ignored.
000 0000–000 0001
000 0010
000 0011–000 1111
001 0000
001 0001
001 0010
001 0011–001 1111
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000–010 1011
010 1100
010 1101
010 1110–010 1111
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110–011 1110
011 1111
100 0000–110 1111
111 0000–111 1001
111 1010–111 1011
111 1100
111 1101
111 1110
1
Causes assertion of the j_en_once _regsel output. Refer to
The OnCE decoder receives as input the 10-bit command from the OCMD and the status signals from the
processor, and generates all the strobes required for reading and writing the selected OnCE registers.
Single-stepping of instructions is performed by placing the CPU in debug mode, scanning appropriate
information into the CPUSCR, and setting the GO bit (with the EX bit cleared) with the RS field indicating
either the CPUSCR or no register selected. After executing a single instruction, the CPU re-enters debug
mode and awaits further commands. During single-stepping, exception conditions may occur if not
9-20
Table 9-7. OCMD Field Descriptions (continued)
Reserved
JTAG ID read–only
Reserved
CPU scan register CPUSCR
No register selected bypass
OnCE control register OCR
Reserved
Instruction address compare 1 IAC1
Instruction address compare 2 IAC2
Instruction address compare 3 IAC3
Instruction address compare 4 IAC4
Data address compare 1 DAC1
Data address compare 2 DAC2
Data Value Compare 1 (DVC1) (e200z335 only)
Data Value Compare 2 (DVC2) (e200z335 only)
Reserved
Debug counter register DBCNT
Debug PCFIFO (PCFIFO) read–only
Reserved
Debug status register DBSR
Debug control register 0 DBCR0
Debug control register 1 DBCR1
Debug control register 2 DBCR2
Debug control register 3 DBCR3
Debug control register 4 DBCR4 (e200z335 only)
Reserved (do not access)
Debug External Resource Control (DBERC0) (e200z335 only)
Reserved (do not access)
General purpose register selects [0–9]
Reserved
Nexus2/3–Access–See
Reserved
1
Enable_OnCE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Chapter 10, "Nexus3 Module."
Section 9.5.5.3, "OnCE Control Register (OCR)."
Freescale Semiconductor