Freescale Semiconductor e200z3 Reference Manual page 330

Power Management
Figure 8-1 is a power management state diagram.
8.1.1 Power Management Signals
Table 8-1 summarizes power management signals. More detailed information is provided in
"Power Management."
Table 8-2. Descriptions of Timer Facility and Power Management Signals
Signal I/O
p_halt I Processor halt request. The active-high p_halt input requests that the core enter the halted state.
p_halted O Processor halted. The active-high p_halted output indicates that the core entered the halted state.
p_stop Processor stop request. The active-high p_stop input requests that the core enter the stopped state.
I
p_stopped Processor stopped. The active-high p_stopped output indicates that the core entered stopped state.
O
p_doze
O Low-power mode. These signals are asserted by the core to reflect the settings of the HID0[DOZE],
p_nap HID0[NAP], and HID0[SLEEP] control bits when MSR[WE] is set. The core can be placed in a low-power
p_sleep state by forcing m_clk to a quiescent state, and brought out of low-power state by re-enabling m_clk . The
time base facilities may be separately enabled or disabled using combinations of the timer facility control
signals.
p_wakeup O Wakeup. Used by external logic to remove the core and system logic from a low-power state. It can also
indicate to the system clock controller that m_clk should be re-enabled for debug purposes.
p_wakeup (or other system state) should be monitored to determine when to release the core (and system
if applicable) from a low-power state.
p_tbdisable I Timer disable. Used to disable the internal time base and decrementer counters. This signal can be used
to freeze the state of the time base and decrementer during low power or debug operation.
p_tbclk I Timer external clock. Used as an alternate clock source for the time base and decrementer counters.
Selection of this clock is made using HID0[SEL_TBCLK] (see
Implementation-Dependent Register 0
p_tbint O Timer interrupt status. Indicates whether an internal timer facility unit is requesting an interrupt
(TSR[WIS] = 1 and TCR[WIE] = 1, or TSR[DIS] = 1 and TCR[DIE] = 1, or
TSR[FIS] = 1 and TCR[FIE] = 1). May be used to exit low-power operation or for other system purposes.
8-2
Active
p_halt | p_stop ~ p_halt & ~ p_stop
Halted
( p_halted asserted)
p_stop ~ p_stop
Power-Down
( p_stopped asserted)
Figure 8-1. Power Management State Diagram
(HID0)").
e200z3 Power Architecture Core Reference Manual, Rev. 2
~ p_halt & ~ p_stop
~ p_stop & p_halt
p_stop
Signal Description
Section 2.13.1, "Hardware
Section 7.5.5,
Freescale Semiconductor