Freescale Semiconductor e200z3 Reference Manual page 17

Figure
Number
6-6 A Load Followed by a Dependent Add Instruction ................................................................ 6-8
6-7 Back-to-Back Load Instructions ............................................................................................. 6-9
6-8 A Load Followed by a Dependent Store Instruction............................................................... 6-9
6-9 Basic Pipeline Flow, Branch Instructions ............................................................................. 6-10
6-10 Basic Pipeline Flow, Branch Speculation ............................................................................. 6-10
6-11 Basic Pipeline Flow, Multi-Cycle Instructions ..................................................................... 6-10
6-12 Pipelined Load/Store Instructions ......................................................................................... 6-11
6-13 Pipelined Load/Store Instructions with Wait-State ............................................................... 6-11
6-14 mtspr, mfspr Instruction Execution—(1) .............................................................................. 6-12
6-15 mtmysr, wrtee, wrteei Instruction Execution...................................................................... 6-12
6-16 DCR, MMU mtspr, mfspr, and MMU Management Instruction Execution ....................... 6-13
6-17 Interrupt Recognition and Handler Instruction Execution.................................................... 6-14
6-18 Interrupt Recognition and Handler Instruction Execution—Load/Store in Progress ........... 6-15
6-19 Interrupt Recognition and Handler Instruction Execution—Multi-Cycle
Instruction Abort .............................................................................................................. 6-16
7-1 Core Signal Groups ................................................................................................................. 7-3
7-2 Example External JTAG Register Design............................................................................. 7-28
7-3 Basic Read Transfer—Single-Cycle Reads, Full Pipelining................................................. 7-32
7-4 Read with Wait-State, Single-Cycle Reads, Full Pipelining ................................................. 7-33
7-5 Basic Write Transfers—Single-Cycle Writes, Full Pipelining.............................................. 7-34
7-6 Write with Wait-state, Single-Cycle Writes, Full Pipelining ................................................ 7-35
7-7 Single-Cycle Reads, Single-Cycle Write, Full Pipelining .................................................... 7-36
7-8 Single-Cycle Read, Write, Read—Full Pipelining................................................................ 7-37
7-9 Multiple-Cycle Reads with Wait-State, Single-Cycle Writes, Full Pipelining ..................... 7-38
7-10 Multi-Cycle Read with Wait-State, Single-Cycle Write, Read with Wait-State, Single-Cycle
Write, Full Pipelining ....................................................................................................... 7-39
7-11 Misaligned Read, Read, Full Pipelining ............................................................................... 7-40
7-12 Misaligned Write, Write, Full Pipelining.............................................................................. 7-41
7-13 Misaligned Write, Single Cycle Read Transfer, Full Pipelining ........................................... 7-42
7-14 Burst Read Transfer .............................................................................................................. 7-43
7-15 Burst Read with Wait-state Transfer ..................................................................................... 7-44
7-16 Burst Write Transfer.............................................................................................................. 7-45
7-17 Burst Write with Wait-State Transfer.................................................................................... 7-46
7-18 Burst Read Transfers............................................................................................................. 7-47
7-19 Burst Read with Wait-State Transfer, Retraction .................................................................. 7-48
7-20 Burst Write Transfers, Single-Beat burst .............................................................................. 7-49
7-21 Read Transfer with Wait-State, Address Retraction ............................................................. 7-50
7-22 Burst Read with Wait-State Transfer, Retraction .................................................................. 7-51
7-23 Read and Write Transfers: Instruction Read with Error, Data Read, Write,
Full Pipelining .................................................................................................................. 7-52
7-24 Data Read with Error, Data Write Retracted, Instruction Read, Full Pipelining .................. 7-53
Freescale Semiconductor
Figures
Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
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3