Freescale Semiconductor e200z3 Reference Manual page 305

m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-8. Single-Cycle Read, Write, Read—Full Pipelining
The first read request (addr
(addr ) is taken at the end of C2 because the first access is terminating (addr
y
cycle is driven in C3, the cycle after the access is taken. Also during C3, a request is generated for a read
to addr , which is taken at the end of C3 because the write access is terminating.
z
During C4, the addr write access is terminated, and no further access is requested.
y
Figure 7-9 shows another sequence of read and write cycles. In this example, reads incur a single wait
state.
Freescale Semiconductor
1 2
nonseq nonseq
addr x addr y
single single
data x
okay
) is taken at the end of cycle C1 because the bus is idle. The first write request
x
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq
addr z
single
data y
okay okay
External Core Complex Interfaces
4 5
idle
data z
okay
). Data for the addr write
x y
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