Freescale Semiconductor e200z3 Reference Manual page 8

Paragraph
Number
5.1 Overview.......................................................................................................................... 5-1
5.1.1 MMU Features............................................................................................................. 5-1
5.1.2 TLB Entry Maintenance Features Summary ............................................................... 5-1
5.2 Effective-to-Real Address Translation............................................................................. 5-2
5.2.1 Effective Addresses ..................................................................................................... 5-4
5.2.2 Address Spaces ............................................................................................................ 5-4
5.2.3 Virtual Addresses and Process ID................................................................................ 5-4
5.2.4 Translation Flow .......................................................................................................... 5-5
5.2.5 Permissions .................................................................................................................. 5-6
5.3 Translation Lookaside Buffer .......................................................................................... 5-7
5.3.1 IPROT Invalidation Protection in TLB1 ..................................................................... 5-8
5.3.2 Replacement Algorithm for TLB1............................................................................... 5-8
5.3.3 The G Bit (of WIMGE) ............................................................................................... 5-9
5.3.4 TLB Entry Field Summary .......................................................................................... 5-9
5.4 Software Interface and TLB Instructions....................................................................... 5-10
5.5 TLB Operations ............................................................................................................. 5-11
5.5.1 Translation Reload ..................................................................................................... 5-11
5.5.2 Reading the TLB........................................................................................................ 5-12
5.5.3 Writing the TLB......................................................................................................... 5-12
5.5.4 Searching the TLB ..................................................................................................... 5-12
5.5.5 TLB Coherency Control ............................................................................................ 5-12
5.5.6 TLB Miss Exception Update ..................................................................................... 5-12
5.5.7 TLB Load on Reset.................................................................................................... 5-13
5.6 MMU Configuration and Control Registers .................................................................. 5-13
5.6.1 MMU Configuration Register (MMUCFG) .............................................................. 5-13
5.6.2 TLB0 and TLB1 Configuration Registers ................................................................. 5-14
5.6.3 Data Exception Address Register (DEAR)................................................................ 5-14
5.6.4 MMU Control and Status Register 0 (MMUCSR0) .................................................. 5-14
5.6.5 MMU Assist Registers (MAS) .................................................................................. 5-14
5.6.5.1 MAS Registers Summary ...................................................................................... 5-14
5.6.5.2 MAS Register Updates .......................................................................................... 5-14
5.7 Effect of Hardware Debug on MMU Operation ............................................................ 5-15
6.1 Overview of Operation .................................................................................................... 6-1
6.1.1 Control Unit ................................................................................................................. 6-2
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Contents
Title
Chapter 5
Memory Management Unit
Chapter 6
Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor