Freescale Semiconductor e200z3 Reference Manual page 368

Nexus3/Nexus2+ Module
Term
JTAG IR and DR sequence
Nexus1
Ownership trace message (OTM)
Public messages
SOC
Standard
Transfer code (TCODE)
Watchpoint
10.1.3 Feature List
The Nexus3 module is compliant with class 3 of the IEEE-ISTO 5001-2003 standard. The following
features are implemented:
• Program trace through branch trace messaging (BTM). Displays program flow discontinuities,
direct and indirect branches, and exceptions, allowing the development tool to interpolate what
transpires between the discontinuities. Thus static code may be traced.
• Data trace by means of data write messaging (DWM) and data read messaging (DRM). DRM and
DWM provide the capability for the development tool to trace reads and/or writes to selected
internal memory resources.
• Ownership trace by means of ownership trace messaging (OTM). Facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An ownership trace
message is transmitted when a new process/task is activated, allowing the development tool to
trace ownership flow.
• Run-time access to embedded processor registers and memory map through the JTAG port. This
allows for enhanced download/upload capabilities.
• Watchpoint messaging through the auxiliary pins
• Watchpoint trigger enable of program and/or data trace messaging
• Auxiliary interface for higher data input/output:
— Configurable, min/max, message data out pins, nex_mdo[n:0]
— One or two message start/end out pins, nex_mseo_b[1:0]
— One read/write ready pin, nex_rdy_b
10-2
Table 10-1. Terms and Definitions (continued)
JTAG instruction register (IR) scan to load an opcode value for selecting a development
register. The JTAG IR corresponds to the OnCE command register (OCMD). The selected
development register is then accessed through a JTAG data register (DR) scan.
The e200z3 (OnCE) debug module. This module integrated with each e200z3 processor
provides all static, core-halted, debug functionality. This module complies with class 1 of
the IEEE-ISTO 5001 standard.
Visibility of process/function that is currently executing.
Messages on the auxiliary pins for meeting common visibility and controllability
requirements.
System-on-a-chip (SOC) signifies all of the modules on a single die. This generally
includes one or more processors with associated peripherals, interfaces, and memory
modules.
The phrase "according to the standard" is used to indicate the IEEE-ISTO 5001 standard.
Message header that identifies the number and/or size of packets to be transferred and
how to interpret each of the packets.
A data or instruction breakpoint that does not cause the processor to halt. Instead, a pin is
used to signal that the condition occurred. A watchpoint message is also generated.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor