Freescale Semiconductor e200z3 Reference Manual page 11

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9.5.5.1 OnCE Status Register (OSR)................................................................................. 9-19
9.5.5.2 OnCE Command Register (OCMD)...................................................................... 9-19
9.5.5.3 OnCE Control Register (OCR).............................................................................. 9-22
9.5.6 Access to Debug Resources....................................................................................... 9-23
9.5.7 Methods for Entering Debug Mode ........................................................................... 9-25
9.5.8 CPU Status and Control Scan Chain Register (CPUSCR) ........................................ 9-26
9.5.8.1 Instruction Register (IR) ........................................................................................ 9-27
9.5.8.2 Control State Register (CTL)................................................................................. 9-27
9.5.8.3 Program Counter Register (PC)............................................................................. 9-30
9.5.8.4 Write-Back Bus Register (WBBR (lower) and WBBR (upper)) (should we consider
making this shorter i.e. WBBRL and WBBRU) ............................................... 9-30
9.5.8.5 Machine State Register (MSR) .............................................................................. 9-31
9.5.9 Instruction Address FIFO Buffer (PC FIFO)............................................................. 9-31
9.5.10 Reserved Registers..................................................................................................... 9-33
9.6 Watchpoint Support ....................................................................................................... 9-33
9.7 MMU and Cache Operation during Debug.................................................................... 9-34
9.8 Cache Array Access During Debug............................................................................... 9-34
9.9 Enabling, Using, and Exiting External Debug Mode: Example .................................... 9-34
10.1 Introduction.................................................................................................................... 10-2
10.1.1 General Description ................................................................................................... 10-2
10.1.2 Terms and Definitions................................................................................................ 10-2
10.1.3 Feature List ................................................................................................................ 10-3
10.2 Enabling Nexus3 Operation........................................................................................... 10-6
10.3 TCODEs Supported ....................................................................................................... 10-7
10.4 Nexus3/Nexus2+ Programmer's Model ..................................................................... 10-11
10.4.1 Client Select Control Register (CSC) ...................................................................... 10-12
10.4.2 Port Configuration Register (PCR).......................................................................... 10-13
10.4.3 Development Control Register 1, 2 (DC1, DC2)..................................................... 10-14
10.4.4 Development Status Register (DS) .......................................................................... 10-16
10.4.5 Read/Write Access Control/Status Register (RWCS).............................................. 10-16
10.4.6 Read/Write Access Data Register (RWD) ............................................................... 10-18
10.4.7 Read/Write Access Address Register (RWA) .......................................................... 10-20
10.4.8 Watchpoint Trigger Register (WT) .......................................................................... 10-20
10.4.9 Data Trace Control Register (DTC)......................................................................... 10-21
10.4.10 Data Trace Start Address 1 and 2 Registers (DTSA1 and DTSA2) ........................ 10-23
10.4.11 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)......................... 10-23
10.5 Nexus3/Nexus2+ Register Access Through JTAG/OnCE........................................... 10-24
Freescale Semiconductor
Contents
Title
Chapter 10
Nexus3/Nexus2+ Module
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
xi