Freescale Semiconductor e200z3 Reference Manual page 254

Instruction Pipeline and Execution Timing
Figure 6-19 shows timing for interrupt recognition and exception processing overhead. This example
shows best-case response timing when an interrupt is received and processed during execution of a
multicycle interruptible instruction.
Time Slot
1
Multi-Cycle
Interruptible
IFETCH
Instruction
Next Instruction
p_extint_b
p_iack
First Instruction of Handler
ec_excp_detected*
update_esr*
update_msr*
oldpc_-> srr0 *
oldmsr_-> srr1 *
* Internal Operations
Figure 6-19. Interrupt Recognition and Handler Instruction Execution—Multi-Cycle
6.7 Instruction Timings
Table 6-2 shows instruction timing for various instruction classes. Pipelined instructions are shown with
cycles of total latency and throughput. Divide instructions are not pipelined and block other instructions
from executing during divide execution.
Load/store multiple instruction cycles are represented as a fixed number of cycles plus a variable number
of cycles where 'n' is the number of words accessed by the instruction. Additionally, cycle times marked
with an ampersand (&) require additional cycles due to serialization.
6-16
2 3 4
DEC EXE Abort
IFETCH DEC Abort
Instruction Abort
e200z3 Power Architecture Core Reference Manual, Rev. 2
5 6 7 8
-- --
-- --
Final Sample Point
IFETCH DEC
9 10
EXE WB
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