Freescale Semiconductor e200z3 Reference Manual page 206

Interrupts and Exceptions
Table 4-17. Floating-Point Unavailable Interrupt Register Settings
Register
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE —
PR 0
ESR Unchanged
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR7[48–59] || 0b0000
4.6.9 System Call Interrupt (IVOR8)
A system call interrupt occurs when a system call (sc, se_sc) is executed and no higher priority exception
exists. Exception extensions implemented in e200z3 for VLE include modification of the system call
interrupt definition to include updating the ESR.
Table 4-18 lists register settings when a system call interrupt is taken.
Register
Set to the effective address of the instruction following the sc instruction.
SRR0
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR [VLEMI]. All other bits cleared.
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR8[48–59] || 0b0000
4.6.10 Auxiliary Processor Unavailable Interrupt (IVOR9)
An APU exception is defined by Book E to occur when an attempt is made to execute an APU instruction
which is implemented but configured as unavailable, and no higher priority exception condition exists.
The e200z3 does not use this interrupt.
4-18
Setting Description
FP 0
ME —
FE0 0
DE —
Table 4-18. System Call Interrupt Register Settings
Setting Description
PR 0
FP 0
ME —
FE0 0
e200z3 Power Architecture Core Reference Manual, Rev. 2
FE1 0
IS 0
DS 0
RI —
DE —
FE1 0
IS 0
DS 0
RI —
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