Freescale Semiconductor e200z3 Reference Manual page 293

Table 7-20 lists interface signals that assist in implementing a real-time development tool capability with
a controller that is external to the
Interface."
Table 7-21 lists the primary JTAG interface signals. These signals are usually connected directly to device
pins (except for j_tdo, which needs tri-state and edge support logic), unless JTAG TAP controllers are
concatenated.
Signal Name Type
j_trst_b
j_tclk
j_tms
j_tdi
j_tdo
j_tdo_en
Table 7-22 describes JTAG interface signals.
Signal I/O
j_tdi
I JTAG/OnCE serial input. Provides data and commands to the OnCE controller. Data is latched on the
rising edge of j_tclk . Data is shifted into the OnCE serial port lsb first.
j_tclk
I JTAG/OnCE serial clock. Supplies the serial clock to the OnCE control block. The serial clock provides
pulses required to shift data and commands into and out of the OnCE serial port (data is clocked into
the OnCE on the rising edge and is clocked out of the OnCE serial port on the rising edge). The debug
serial clock frequency must not exceed 50% of the processor clock frequency.
Freescale Semiconductor
. These signals are described in
core
Table 7-20. core Development Support (Nexus3) Signals
Signal Type
nex_mcko O
nex_rdy_b
O
nex_evto_b
O
nex_evti_b
I
nex_mdo[n:0]
O
nex_mseo_b[1:0] O
Table 7-21. JTAG Primary Interface Signals
I JTAG test reset
I JTAG test clock
I JTAG test mode select
I JTAG test data input
O Test data out to master controller or pad
Enables TDO output buffer. j_tdo_en is asserted when the
O
TAP controller is in the shift_dr or shift_ir state.
Table 7-22. Descriptions of JTAG Interface Signals
e200z3 Power Architecture Core Reference Manual, Rev. 2
Section 10.11, "Nexus3/Nexus2+ Pin
Description
Nexus3 clock output
Nexus3 ready output
Nexus3 event-out output
Nexus3 event-in input
Nexus3 message data output
Nexus3 message start/end output
Description
Signal Description
External Core Complex Interfaces
7-25