Freescale Semiconductor e200z3 Reference Manual page 296

External Core Complex Interfaces
Table 7-22. Descriptions of JTAG Interface Signals (continued)
Signal I/O
j_serial_data I Serial data. Receives serial data from external JTAG registers. All external registers share this serial
output back to the core. Therefore it must be muxed using j_gp_regsel[0:11] , j_lsrl_regsel , and
j_en_once_regsel . The data is internally routed to j_tdo .
j_key_in I Key data in. Receives serial data from logic to indicate a key or other value to be scanned out in the
Shift_IR state when the current value in the IR is the Enable_OnCE instruction. This input is provided
to assist in implementing security logic outside of the core, which conditionally asserts jd_en_once .
During the Shift_IR state, when jd_en_once is negated, this input is sampled on the rising edge of
j_tclk , and, after a 2-clock delay, the data is internally routed to j_tdo . This allows provision of a key
value via the j_tdo output following a transition from Capture_IR to Shift_IR. j_key_in provides the key
value.
Figure 7-2 shows an example for designing an external JTAG register set using the inputs and outputs
provided along with the JTAG primary inputs. The main components are a clock generation unit, a JTAG
shifter (load, shift, hold, clr), the registers (load, hold, clr), and an input mux to the shifter for the serial
output back to the core.The shifter and the registers may be as wide as the application warrants [0:x]. The
length determines the number of states the TAP controller is held in Shift_DR (x+1).
j_capture_dr
j_tclk
j_gp_regsel[1:0]
j_capture_dr
j_shift_dr
j_update_gp_reg
NOTES:
clk_shfter = j_tclk & (j_shift_dr | j_capture_dr)
1.
clk_reg0 = j_tclk & j_update_gp_reg & j_gp_regsel[0]
2.
clk_reg1 = j_tclk & j_update_gp_reg & j_gp_regsel[1]
3.
7-28
j_gp_regsel[1:0]
j_tdi
j_shift_dr
1
clk_shfter
2
clk_reg0
CLK
GEN
3
clk_reg1
j_trst_b
Figure 7-2. Example External JTAG Register Design
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal Description
1 0
S
SI
D
SHIFT
Shifter
LOAD
Q
Data
D
REG0
Q
D
REG1
Q
j_serial_data
SO
reg0_dat
reg1_dat
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