Freescale Semiconductor e200z3 Reference Manual page 428

Glossary
Fraction. In the binary representation of a floating-point number, the field of the
significand that lies to the right of its implied binary point.
G
General-purpose register (GPR). Any of the 32 registers in the general-purpose register
file. These registers provide the source operands and destination results for all
integer data manipulation instructions. Integer load instructions move data from
memory to GPRs and store instructions move data from GPRs to memory.
Guarded. The guarded attribute pertains to out-of-order execution. When a page is
designated as guarded, instructions and data cannot be accessed out-of-order.
H
Harvard architecture. An architectural model featuring separate caches and other
memory management resources for instructions and data.
Hashing. An algorithm used in the page table search process.
I
IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that
defines operations and representations of binary floating-point numbers.
Illegal instructions. A class of instructions that are not implemented for a particular
PowerPC processor. These include instructions not defined by the PowerPC
architecture. In addition, for 32-bit implementations, instructions that are defined
only for 64-bit implementations are considered to be illegal instructions. For
64-bit implementations instructions that are defined only for 32-bit
implementations are considered to be illegal instructions.
Implementation. A particular processor that conforms to the PowerPC architecture, but
may differ from other architecture-compliant implementations for example in
design, feature set, and implementation of optional features. The PowerPC
architecture has many different implementations.
Imprecise interrupt. A type of synchronous interrupt that is allowed not to adhere to the
precise interrupt model (see Precise interrupt). The PowerPC architecture allows
only floating-point exceptions to be handled imprecisely.
Instruction queue. A holding place for instructions fetched from the current instruction
stream.
Integer unit. The functional unit in the processor responsible for executing all integer
instructions.
In-order. An aspect of an operation that adheres to a sequential model. An operation is
said to be performed in-order if, at the time that it is performed, it is known to be
required by the sequential execution model. See Out-of-order.
Instruction latency. The total number of clock cycles necessary to execute an instruction
and make ready the results of that instruction.
Glossary-4
e200z3 Power Architecture Core Reference Manual, Rev. 2
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