Freescale Semiconductor e200z3 Reference Manual page 199

Table 4-9. Critical Input Interrupt Register Settings (continued)
Register
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR0[48–59] || 0b0000 (autovectored)
IVPR[32–47] || p_voffset[0:11] || 0b0000 (non-autovectored)
1
DE is cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the debug APU
is enabled.
2
RI is cleared by all critical class interrupts using CSRR0/1 and the machine check interrupt. These interrupt handlers
should set RI early in the handler after CSRR0/1 have been saved to allow for improved recoverability.
When the debug APU is enabled, MSR[DE] is not automatically cleared by a critical input interrupt but
can be configured to be cleared through HID0 (HID0[CICLRDE]). Refer to
Implementation-Dependent Register 0 (HID0)."
IVOR0 is the vector offset register used by autovectored critical input interrupts to determine the interrupt
handler location. The e200z3 also provides the capability to directly vector critical input interrupts to
multiple handlers by allowing a critical input interrupt request to be accompanied by a vector offset. The
p_voffset[0:11] inputs are used in place of the value in IVOR0 to form the interrupt vector when a critical
input interrupt request is not autovectored (p_avec_b negated when p_critint_b asserted).
4.6.2 Machine Check Interrupt (IVOR1)
The e200z3 implements the machine check exception as defined in Book E except for automatic clearing
of MSR[DE]. The e200z3 initiates a machine check interrupt if MSR[ME]=1 and any of the machine
check sources listed in Table 4-2
is cleared, in which case the processor generates an internal checkstop condition and enters checkstop
state. When a processor is in checkstop state, instruction processing is suspended and generally cannot
continue without restarting the processor. Note that other conditions may lead to the checkstop condition;
the disabled machine check exception is only one of these.
The e200z3 implements MCSR to record the sources of machine checks. See
Check Syndrome Register (MCSR),"
MSR[DE] is not automatically cleared by a machine check exception but can be configured to be cleared
or left unchanged through HID0[MCCLRDE]. See
Register 0 (HID0)."
4.6.2.1 Machine Check Interrupt Enabled (MSR[ME]=1)
Machine check interrupts are enabled when MSR[ME]=1. When a machine check interrupt is taken,
registers are updated as shown in
Freescale Semiconductor
Setting Description
is detected. As defined in Book E, the interrupt is not taken if MSR[ME]
for more information.
Section 2.13.1, "Hardware Implementation-Dependent
Table 4-10.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
Section 2.13.1, "Hardware
Section 4.4.1, "Machine
4-11