Freescale Semiconductor e200z3 Reference Manual page 16

Figure
Number
2-35 DBCR2 Register ................................................................................................................... 2-40
2-36 DBCR3 Register ................................................................................................................... 2-43
2-37 DBSR Register ...................................................................................................................... 2-47
2-38 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-49
2-39 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-51
2-40 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-52
2-41 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-53
2-42 MMU Configuration Register 1 (MMUCFG) ...................................................................... 2-53
2-43 TLB Configuration Register 0 (TLB0CFG) ......................................................................... 2-54
2-44 TLB Configuration Register 1 (TLB1CFG) ......................................................................... 2-55
2-45 MAS Register 0 (MAS0) Format.......................................................................................... 2-56
2-46 MMU Assist Register 1 (MAS1) .......................................................................................... 2-56
2-47 MMU Assist Register 2 (MAS2) .......................................................................................... 2-57
2-48 MMU Assist Register 3 (MAS3) .......................................................................................... 2-58
2-49 MMU Assist Register 4 (MAS4) .......................................................................................... 2-59
2-50 MMU Assist Register 6 (MAS6)) ......................................................................................... 2-60
2-51 Process ID Register (PID0)................................................................................................... 2-60
2-52 Context Control Register (CTXCR) ..................................................................................... 2-61
2-53 Parallel Signature Control Register (PSCR) ......................................................................... 2-68
2-54 Parallel Signature Status Register (PSSR) ............................................................................ 2-69
2-55 Parallel Signature High Register (PSHR) ............................................................................. 2-70
2-56 Parallel Signature Low Register (PSLR) .............................................................................. 2-70
2-57 Parallel Signature Counter Register (PSCTR) ...................................................................... 2-70
2-58 Parallel Signature Update High Register (PSUHR).............................................................. 2-71
2-59 Parallel Signature Update Low Register (PSULR)............................................................... 2-71
4-1 Exception Syndrome Register (ESR)...................................................................................... 4-4
4-2 Machine State Register (MSR) ............................................................................................... 4-5
4-3 Machine Check Syndrome register (MCSR) .......................................................................... 4-7
4-4 Interrupt Vector Prefix Register (IVPR) ................................................................................. 4-8
4-5 Interrupt Vector Offset Registers (IVOR) ............................................................................... 4-9
5-1 Effective-to-Real Address Translation Flow........................................................................... 5-3
5-2 Virtual Address and TLB-Entry Compare Process ................................................................. 5-5
5-3 Granting of Access Permission ............................................................................................... 5-7
5-4 e200z3 TLB1 Organization..................................................................................................... 5-8
5-5 Victim Selection ...................................................................................................................... 5-9
5-6 MMU Assist Registers Summary ......................................................................................... 5-14
6-1 e200z3 Block Diagram............................................................................................................ 6-2
6-2 Pipeline Diagram..................................................................................................................... 6-4
6-3 Instruction Buffers .................................................................................................................. 6-6
6-4 Branch Target Buffer............................................................................................................... 6-7
6-5 Basic Pipeline Flow, Single-Cycle Instructions ...................................................................... 6-8
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Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor