Freescale Semiconductor e200z3 Reference Manual page 338

Debug Support
• Instruction complete debug events
• Interrupt taken debug events
• Return debug events
• Unconditional debug events
These events are described in further detail in the EREF.
The core defines the following debug events, which are described in
• The debug counter debug events DCNT1 and DCNT2
• The external debug events DEVT1 and DEVT2
• The critical interrupt taken debug event (CIRPT)
• The critical return debug event (CRET)
The core debug framework supports most of these event types. The following Book E–defined
functionality is not supported:
• Instruction address compare and data address compare real address mode
• Data value compare mode
A brief description of each of the debug event types is shown in
and DSRR1 are used to store the address of the instruction following a load or store, assuming that the
debug APU is enabled. If it is disabled, CSRR0 is used.
9-6
e200z3 Power Architecture Core Reference Manual, Rev. 2
Table 9-2:
Table 9-2. In these descriptions, DSRR0
Freescale Semiconductor