Freescale Semiconductor e200z3 Reference Manual page 239

Chapter 6
Instruction Pipeline and Execution Timing
This chapter describes the instruction pipeline and instruction timing information. The core is partitioned
into the following systems:
• Instruction unit
• Control unit
• Integer unit
• Load/store unit
• Core interface
6.1 Overview of Operation
Figure 6-1 shows a block diagram of the e200z3 core. The instruction fetch unit prefetches instructions
from memory into the instruction buffers. The decode unit decodes each instruction and generates
information needed by the branch and execution units. Branch target instructions are written into the
branch target prefetch buffers; sequentially prefetched instructions are written into the instruction buffers.
The instruction fetch unit attempts to supply a constant stream of instructions to the execution pipeline. It
does so by decoding and detecting branches early in the instruction buffer, making branch predictions, and
prefetching their branch targets into the instruction buffer. By prefetching the branch targets early, some
or all of the branch pipeline bubbles can be hidden from the execution pipeline.
The instruction issue unit attempts to issue a single instruction each cycle to one of the execution units.
Source operands for each of the instructions are provided from the GPRs or from the operand feed-forward
muxes. Data or resource hazards may create conditions that stall instruction issue until the hazard is
eliminated.
The execution units write the result of a finished instruction onto the proper result bus and into the
destination registers. The writeback logic retires an instruction when the instruction has finished
execution. Up to two results can be simultaneously written.
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
6-1