Freescale Semiconductor e200z3 Reference Manual page 420

Nexus3/Nexus2+ Module
Table 10-38 shows examples of direct branch messages: one with 2 MDO/1 MSEO, and one with 8
MDO/2 MSEO.
Table 10-37. Direct Branch Message Example (2 MDO/1 MSEO)
Clock
1
T0 and I0 are the least-significant bits, where Tx = TCODE number (fixed);
Sx = Source processor (fixed); Ix = Number of instructions (variable);
Ax = Unique portion of the address (variable).
Table 10-38. Direct Branch Message Example (8 MDO / 2 MSEO)
Clock
0 X X
1 S1 S0
2 0 0
3 S1 S0
1
T0 and I0 are the least-significant bits, where Tx = TCODE number (fixed); Sx = Source processor (fixed);
Ix = Number of instructions (variable); Ax = Unique portion of the address (variable).
Table 10-39 shows an example of a data write message with 8 MDO/1 MSEO configuration, and
Table 10-40 shows the same DWM with 8 MDO/2 MSEO configuration.
Table 10-39. Data Write Message Example (8 MDO/1 MSEO)
Clock
0 X X
1 S1 S0
2 A2 A1
3 D7 D6
4 0 0
5 0 0
1
T0, A0, D0 are the least-significant bits, where Tx = TCODE number (fixed); Sx = Source processor (fixed);
Zx = Data size (fixed); Ax = Unique portion of the address (variable); Dx = Write data (variable-8, 16 or 32-bit).
10-54
nex_mdo[1:0] nex_mseo_b
0 X X
1 T1 T0
2 T3 T2
3 T5 T4
4 S1 S0
5 S3 S2
6 I1 I0
7 0 0
nex_mdo[7:0]
X X X X X
T5 T4 T3 T2 T1
0 0 I1 I0 S3
T5 T4 T3 T2 T1
nex_mdo[7:0]
X X X X
T5 T4 T3 T2 T1
A0 Z2 Z1 Z0 S3
D5 D4 D3 D2 D1
0 0 0 0
0 0 0 0
e200z3 Power Architecture Core Reference Manual, Rev. 2
State
1 Idle (or end of last message)
0 Start message
0 Normal transfer
0 Normal transfer
0 Normal transfer
0 Normal transfer
1 End packet
1 End message
nex_mseo_b[1:0]
X 1 1
T0 0 0
S2 1 1
T0 0 0
nex_mseo_b
X X 1 Idle (or end of last message)
T0 0 Start message
S2 1 End packet
D0 0 Normal transfer
0 0 1 End packet
0 0 1 End message
1
1
State
Idle (or end of last message)
Start message
End packet/end message
Start message
1
State
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