Freescale Semiconductor e200z3 Reference Manual page 220

Interrupts and Exceptions
4.8 Interrupt Processing
When an interrupt is taken, SRR0/SRR1 for non-critical interrupts, CSRR0/CSRR1 for critical interrupts,
and either CSRR0/CSRR1 or DSRR0/DSRR1 for debug interrupts are used to save the contents of the
MSR and to help identify where instruction execution should resume after the interrupt is handled.
When an interrupt occurs, one of SRR0/CSRR0/DSRR0 is set to the address of the instruction that caused
the exception or to the following instruction if appropriate.
SRR1 is used to save machine state (selected MSR bits) on non-critical interrupts and to restore those
values when an rfi executes. CSRR1 is used to save machine status (selected MSR bits) on critical
interrupts and to restore those values when an rfci instruction is executed. DSRR1 is used to save machine
status (selected MSR bits) on debug interrupts when the debug APU is enabled and to restore those values
when an rfdi executes.
The ESR is loaded with information specific to the exception type. Some interrupt types can only be
caused by a single exception type and thus do not use an ESR setting to indicate the interrupt cause.
The MSR is updated to preclude unrecoverable interrupts from occurring during the initial portion of the
interrupt handler. Specific settings are described in
For alignment, data storage, or data TLB miss interrupts, or for a machine check due to cache parity error
on data access interrupts, the data exception address register (DEAR) is loaded with the address that caused
the interrupt to occur.
For machine check interrupts, the MCSR is loaded with information specific to the exception type.
Instruction fetch and execution resume, using the new MSR value, at a location specific to the exception
type. The location is determined by the IVPR and an IVOR specific for each type of interrupt (see
Table 4-2). A new operating context is selected using the low-order three bits of the specific IVOR selected
by the type of interrupt.
Table 4-33 shows the MSR settings for different interrupt categories. Note that reserved and preserved
MSR bits are unimplemented and are read as 0.
Bits MSR Definition Reset Setting Non-Critical Interrupt Critical Interrupt Debug Interrupt
37 UCLE
38 SPE
45 WE
46 CE
48 EE
49 PR
50 FP
51 ME
52 FE0
4-32
Table 4-33. MSR Setting Due to Interrupt
0
0
0
0
0
0
0
0
0
e200z3 Power Architecture Core Reference Manual, Rev. 2
Table 4-33.
0 0
0 0
0 0
— 0
0 0
0 0
0 0
— —
0 0
0
0
0
1
—/0
1
—/0
0
0
—
0
Freescale Semiconductor