Freescale Semiconductor e200z3 Reference Manual page 250

Instruction Pipeline and Execution Timing
Time Slot
Previous Instruction (Multicycle)
mtspr, mfspr
Next Instruction
Figure 6-15 applies to the mtmsr, wrtee, and wrteei instructions. Execution of subsequent instructions
stalls until these instructions writeback.
Time Slot
Previous Instruction
mtmsr, wrtee, wrteei
Next Instruction
Access to MMU SPRs stalls until all outstanding bus accesses complete and the MMU is idle
(p_[i,d]_cmbusy negated) to allow an access window where no translations or cache cycles are required.
Figure 6-16 shows an example where an outstanding bus access delays mtspr/mfspr execution until the
bus becomes idle. Processor access requests are held off during execution of an MMU SPR instruction. A
subsequent access request may be generated in the WB cycle. This same protocol applies to MMU
management instructions (such as tlbre, tlbwe, etc.) as well as to the DCRs.
6-12
IFETCH DEC
IFETCH
IFETCH
Figure 6-14. mtspr, mfspr Instruction Execution—(1)
IFETCH DEC
IFETCH
Figure 6-15. mtmysr, wrtee, wrteei Instruction Execution
e200z3 Power Architecture Core Reference Manual, Rev. 2
. . .
EXE1 EXEn WB
DEC Stall . . . EXE
. . .
Stall DEC
EXE WB
DEC EXE WB
IFETCH DEC Stall
WB
Stall EXE WB
WB
EXE
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