Freescale Semiconductor e200z3 Reference Manual page 192

Interrupts and Exceptions
Interrupt Type IVOR n
Instruction TLB error 14
Debug 15
Reserved 6–31
SPE unavailable 32
SPE data 33
SPE round 34
1
Vector to [p_rstbase[0:19]] || 0xFFC in e200z3. Vector to [p_rstbase[0:29]] || 2'b00 in e200z335.
2
Autovectored external and critical input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly.
4.3 Exception Syndrome Register (ESR)
ESR, shown in Figure 4-1, provides a syndrome to distinguish exceptions that can generate the same
interrupt type. The e200z3 adds some implementation-specific bits to this register.
32 35 36 37
Field — PIL PPR PTR FP ST — DLK ILK AP PUO BO PIE
Reset
R/W
SPR
The ESR fields are described in
Bit(s) Name
32–35 — Reserved, should be cleared.
36 PIL Illegal instruction exception
37 PPR Privileged instruction exception
38 PTR Trap exception
39 FP Floating-point operation
40 ST Store operation
41 — Reserved, should be cleared.
42 DLK Data cache locking
43 ILK Instruction cache locking
4-4
Table 4-2. Exceptions and Conditions (continued)
Instruction translation lookup did not match a valid TLB entry.
Trap, instruction address compare, data address compare, instruction complete,
branch taken, return from interrupt, interrupt taken, debug counter, external
debug event, unconditional debug event
—
See Section 4.6.18, "SPE APU Unavailable Interrupt (IVOR32)."
See Section 4.6.19, "SPE Floating-Point Data Interrupt (IVOR33)."
See Section 4.6.20, "SPE Floating-Point Round Interrupt (IVOR34)."
38 39 40 41 42 43 44
Figure 4-1. Exception Syndrome Register (ESR)
Table 4-3.
Table 4-3. ESR Field Descriptions
Description
1
e200z3 Power Architecture Core Reference Manual, Rev. 2
Cause
45 46 47 48 55 56
— SPE — VLEMI
All zeros
R/W
SPR 62
Associated Interrupt Type
—
Program
Program
Program
Alignment, data storage, data TLB, program
Alignment, data storage, data TLB
—
Data storage
Data storage`
Section/Page
4.6.15/4-21
4.6.16/4-22
—
4.6.18/4-26
4.6.19/4-27
4.6.20/4-27
57 58 59 61 62 63
— MIF XTE
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