Freescale Semiconductor e200z3 Reference Manual page 395

Power architecture core
Table of Contents

Advertisement

When the CPU enters a low power mode in which instructions are no longer executed, a PCM is
generated. The instruction count and history information provided by the PCM can be used to
determine the last sequence of instructions executed prior to low-power mode entry.
Whenever program trace is disabled by any means, a PCM is generated. The instruction count and
history information provided by the PCM can be used to determine the last sequence of instructions
executed prior to disabling program trace. A second PCM is generated on this event if there has
been an execution mode switch into or out of a sequence of VLE instructions. This VLE state
information allows the development tool to interpret any preceding instruction count or history
information in the proper context.
Whenever the CPU crosses a page boundary that results in an execution mode switch into or out
of a sequence of VLE instructions, a PCM is generated. The PCM effectively breaks up any
running instruction count and history information between the two modes of operation so that the
instruction count and history information can be processed by the development tool in the proper
context.
When using program trace in history mode, when a direct branch results in an execution mode
switch into or out of a sequence of VLE instructions, a PCM is generated. The PCM effectively
breaks up any running history information between the two modes of operation so that the history
information can be processed by the development tool in the proper context.
Program correlation is messaged out in the format shown in
(1–32 bits)
Branch History
10.7.2.7
BTM Overflow Error Messages
An error message occurs when the message queue is full and a new message cannot be queued. The FIFO
discards incoming messages until it has completely emptied the queue. Once emptied, an error message is
queued. The error encoding indicates which types of messages attempted to be queued while the FIFO was
being emptied.
If only a program trace message attempts to enter the queue while it is being emptied, the error message
incorporates the program trace only error encoding, 00001. If both OTM and program trace messages
attempt to enter the queue, the error message incorporates the OTM and program trace error encoding
00111. If a watchpoint also attempts to be queued while the FIFO is being emptied, the error message
incorporates error encoding 01000.
DC1[OVC] can be set to delay the CPU in order to alleviate, but not
eliminate, potential overrun situations.
Freescale Semiconductor
(1–8 bits)
Sequence Count ECODE Source Process TCODE (100001)
Maximum length = 54 bits; minimum length = 16 bits
Figure 10-23. Program Correlation Message Format
NOTE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Figure
10-23:
(4 bits)
(4 bits)
Nexus3/Nexus2+ Module
(6 bits)
10-29

Advertisement

Table of Contents
loading

Table of Contents