Freescale Semiconductor e200z3 Reference Manual page 194

Interrupts and Exceptions
Bits Name
32–36 — Reserved, should be cleared.
37 UCLE User cache lock enable. (Implemented, but ignored by e200z3)
0 Execution of the cache locking instructions in user mode (MSR[PR] = 1) disabled; data storage interrupt
taken instead, and ILK or DLK is set in the ESR.
1 Execution of the cache lock instructions in user mode enabled
38 SPE SPE available
0 Execution of SPE APU vector instructions is disabled; SPE Unavailable exception taken instead, and
ESR[SPE] is set.
1 Execution of SPE APU vector instructions is enabled.
39–44 — Reserved, should be cleared.
45 WE Wait state (power management) enable. Defined as optional by Book E and implemented in the e200z3.
0 Power management is disabled.
1 Power management is enabled. The processor can enter a power-saving mode when additional conditions
are present. The mode chosen is determined by HID0[DOZE,NAP,SLEEP], described in
"Hardware Implementation-Dependent Register 0 (HID0)."
46 CE Critical interrupt enable
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
47 — Preserved
48 EE External interrupt enable
0 External Input, decrementer, and fixed-interval timer interrupts are disabled.
1 External input, decrementer, and fixed-interval timer interrupts are enabled.
49 PR Problem state
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for
example, GPRs, SPRs, MSR, etc.).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged
resource.
50 FP Floating-point available
0 Floating-point unit is unavailable. The processor cannot execute floating-point instructions, including
floating-point loads, stores, and moves. (An FP unavailable interrupt is generated on attempted execution of
floating-point instructions).
1 Floating-point unit is available. The processor can execute floating-point instructions. (Note that for the
e200z3, the floating-point unit is not supported; an unimplemented operation exception is generated for
attempted execution of floating-point instructions when FP is set).
51 ME Machine check enable
0 Machine check interrupts are disabled. Checkstop mode is entered when p_mcp_b is recognized asserted
or an ISI or ITLB exception occurs on a fetch of the first instruction of an exception handler.
1 Machine check interrupts are enabled.
52 FE0 Floating-point exception mode 0 (not used by the e200z3)
53 — Reserved, should be cleared.
54 DE Debug interrupt enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] is set.
55 FE1 Floating-point exception mode 1 (not used by the e200z3)
4-6
Table 4-4. MSR Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Section 2.13.1,
Freescale Semiconductor