Freescale Semiconductor e200z3 Reference Manual page 232

Memory Management Unit
Field
SIZE[0–3] Encoded page size
0000 Reserved
0001 4 Kbytes
0010 16 Kbytes
0011 64 Kbytes
0100 256 Kbytes
0101 1 Mbyte
0110 4 Mbytes
0111 16 Mbytes
1000 64 Mbytes
1001 256 Mbytes
All others—reserved
SX, SW, SR Supervisor execute, write, and read permission bits
UX, UW, UR User execute, write, and read permission bits
WIMGE Memory/cache attributes (write-through, cache-inhibit, memory coherence required, guarded, endian)
U0–U3 User attribute bits—used only by software
IPROT Invalidation protection
VLE VLE page indicator
5.4 Software Interface and TLB Instructions
TLB1 is accessed indirectly through several MMU assist (MAS) registers, which software can write and
read with mtspr and mfspr instructions. MAS registers contain information related to reading and writing
a given entry within TLB1. Data is read from the TLB into the MAS registers with a tlbre (TLB Read
Entry) instruction and is written to the TLB from the MAS registers with a tlbwe (TLB Write Entry)
instruction.
Certain fields of the MAS registers are also written by hardware when an instruction TLB error, data TLB
error, DSI, or ISI interrupt occurs.
On a TLB error interrupt, the MAS registers are written by hardware with the proper EA, default attributes
(TID, WIMGE, permissions, and so on), TLB selection information, and an entry in the TLB to replace.
Software manages this entry selection information by updating a replacement entry value during TLB miss
handling. Software must provide the correct RPN and permission information in one of the MAS registers
before executing a tlbwe instruction.
On taking a DSI or ISI interrupt, hardware updates only the search PID (SPID) and search address space
(SAS) fields in the MAS registers, using the contents of PID0 and the corresponding MSR[IS] or
MSR[DS] value used when the data or instruction storage interrupt was recognized. During the interrupt
handler, software can issue a TLB Search Instruction (tlbsx), which uses the SPID field along with the
SAS field, to determine the entry related to the data or instruction storage interrupt. Note that it is possible
that the entry that caused the data or instruction storage interrupt no longer exists in the TLB by the time
the search occurs if a TLB invalidate or replacement removes the entry between the time the exception is
recognized and when the tlbsx is executed.
5-10
Table 5-3. TLB Entry Bit Fields for e200z3 (continued)
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor