Freescale Semiconductor e200z3 Reference Manual page 9

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Number
6.1.2 Instruction Unit ............................................................................................................ 6-2
6.1.3 Branch Unit.................................................................................................................. 6-3
6.1.4 Instruction Decode Unit............................................................................................... 6-3
6.1.5 Exception Handling ..................................................................................................... 6-3
6.2 Execution Units................................................................................................................ 6-3
6.2.1 Integer Execution Unit................................................................................................. 6-3
6.2.2 Load/Store Unit............................................................................................................ 6-3
6.3 Instruction Pipeline .......................................................................................................... 6-4
6.3.1 Description of Pipeline Stages ..................................................................................... 6-4
6.3.2 Instruction Buffers ....................................................................................................... 6-5
6.3.3 Single-Cycle Instruction Pipeline Operation ............................................................... 6-7
6.3.4 Basic Load and Store Instruction Pipeline Operation.................................................. 6-8
6.3.5 Change-of-Flow Instruction Pipeline Operation.......................................................... 6-9
6.3.6 Basic Multi-Cycle Instruction Pipeline Operation..................................................... 6-10
6.3.7 Additional Examples of Instruction Pipeline Operation for Load and Store............. 6-10
6.3.8 Move to/from SPR Instruction Pipeline Operation.................................................... 6-11
6.4 Stalls Caused by Accessing SPRs.................................................................................. 6-13
6.5 Instruction Serialization ................................................................................................. 6-13
6.6 Interrupt Recognition and Exception Processing........................................................... 6-14
6.7 Instruction Timings ........................................................................................................ 6-16
6.7.1 SPE and Embedded Floating-Point Instruction Timing............................................. 6-21
6.7.1.1 SPE Integer Simple Instructions Timing ............................................................... 6-22
6.7.1.2 SPE Load and Store Instruction Timing ................................................................ 6-23
6.7.1.3 SPE Complex Integer Instruction Timing ............................................................. 6-24
6.7.1.4 Vector Floating-Point APU Instruction Timing..................................................... 6-27
6.7.1.5 SPE Scalar Floating-Point Instruction Timing ...................................................... 6-28
6.8 Operand Placement on Performance.............................................................................. 6-29
7.1 Overview.......................................................................................................................... 7-1
7.2 Signal Index ..................................................................................................................... 7-2
7.3 Signal Descriptions .......................................................................................................... 7-7
7.3.1 Processor State Signals .............................................................................................. 7-20
7.3.2 JTAG ID Signals ........................................................................................................ 7-29
7.4 Internal Signals .............................................................................................................. 7-30
7.5 Timing Diagrams ........................................................................................................... 7-30
7.5.1 Processor Instruction/Data Transfers ......................................................................... 7-30
7.5.1.1 Basic Read Transfer Cycles ................................................................................... 7-32
7.5.1.2 Read Transfer with Wait State ............................................................................... 7-33
Freescale Semiconductor
Contents
Title
Chapter 7
External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
ix