Freescale Semiconductor e200z3 Reference Manual page 314

External Core Complex Interfaces
Figure 7-15 shows functional timing for a burst write with wait-state transfer.
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
The first cycle of the burst incurs a single wait-state. Data for the second beat of the burst is valid the cycle
after the second beat is taken.
7-46
Burst Write with Wait-state
1 2
nonseq seq
addr x addr x+8
data x
okay okay
Figure 7-17. Burst Write with Wait-State Transfer
e200z3 Power Architecture Core Reference Manual, Rev. 2
3 4
seq
addr x+16
incr
data x+8
okay okay
5 6 7
seq ...
addr x+24
data x+16 data x+24
okay okay
Freescale Semiconductor