Freescale Semiconductor e200z3 Reference Manual page 410

Nexus3/Nexus2+ Module
3. Initialize RWD using the Nexus register index of 0xA; see
— Write data = 0xnnnn_nnnn (write data)
4. The Nexus block then arbitrates for the AHB system bus and transfers the data value from the data
buffer RWD register to the memory-mapped address in RWA. When the access has completed
without error (ERR=0), Nexus asserts the nex_rdy_b signal (see
nex_rdy_b) and clears RWCS[DV]. This indicates that the device is ready for the next access.
Only the nex_rdy_b signal and the DV and ERR fields within RWCS
provide read/write access status to the external development tool.
10.10.2 Block Write Access (Non-Burst Mode)
1. For a non-burst block write access, follow Steps 1, 2, and 3 outlined in
Write Access," to initialize the registers, but use a value greater than one (0x0001) for
RWCS[CNT].
2. The Nexus block then arbitrates for the AHB system bus and transfers the first data value from the
RWD register to the memory-mapped address in RWA. When the transfer has completed without
error (ERR = 0), the address from the RWA register is incremented to the next word size (specified
in RWCS[SZ]), and the number from the CNT field is decremented. Nexus then asserts the
nex_rdy_b pin. This indicates that the device is ready for the next access.
3. Repeat step 3 in
When this occurs, RWCS[DV] is cleared to indicate the end of the block write access.
10.10.3 Block Write Access (Burst Mode)
1. For a burst block write access, follow steps 1 and 2 outlined in
Access," to initialize the registers, using a value of four (double-word) for RWCS[CNT] and an
RWCS[SZ] value of 0b011, indicating 64-bit access.
2. Initialize the burst data buffer (RWD register) through the access method outlined in
"Nexus3/Nexus2+ Register Access Through JTAG/OnCE,"
see Table 10-7.
3. Repeat step 2 until all double-word values are written to the buffer.
The data values must be shifted in 32 bits at a time, least significant bit first
(that is, double-word write = two word writes to RWD).
4. The Nexus block then arbitrates for the AHB system bus and transfers the burst data values from
the data buffer to the AHB beginning from the memory mapped address in RWA. For each access
within the burst, the address from the RWA register is incremented to the next double-word size
(as specified in RWCS[SZ]), modulo the length of the burst, and the number from the CNT field is
decremented.
5. When the entire burst transfer has completed without error (ERR=0), Nexus3/Nexus2+ then asserts
the nex_rdy_b pin, and RWCS[DV] is cleared to indicate the end of the block write access.
10-44
Section 10.10.1, "Single Write Access,"
e200z3 Power Architecture Core Reference Manual, Rev. 2
Table 10-7. Configure as shown below:
Table 10-31
NOTE
until the internal CNT value is zero.
Section 10.10.1, "Single Write
using the Nexus register index of 0xA;
NOTE
for detail on
Section 10.10.1, "Single
Section 10.5,
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