Freescale Semiconductor e200z3 Reference Manual page 247

Time Slot
First Load Instruction
Second Load Instruction
When a load is followed by a load or a store instruction that depends on the first load data for EA
calculation, a pipeline stall is incurred.
followed by a dependent store instruction through EA calculation. The second store instruction in this case
is dependent on the first load instruction for its EA calculation.
Time Slot
First Load Instruction
Second Store Instruction
Figure 6-8. A Load Followed by a Dependent Store Instruction
A store instruction that depends on its previous load for its store data does not stall the pipeline.
6.3.5 Change-of-Flow Instruction Pipeline Operation
A branch instruction takes either one or 2 cycles to execute. Simple change of flow instructions require
2 cycles to refill the pipeline with the target instruction for taken branches and branch and link instructions
with no prediction.
For branch-type instructions, in some situations, this 2-cycle timing may be reduced by performing the
target fetch speculatively while the branch instruction is still being fetched into the instruction buffer. The
branch target address is obtained from the BTB. The resulting branch timing reduces to a single clock
when the target fetch is initiated early enough and the branch is taken.
for branch instructions.
Freescale Semiconductor
IFETCH DEC / EA
IFETCH
Figure 6-7. Back-to-Back Load Instructions
Figure 6-8 shows the instruction flow for a load instruction
IFETCH DECODE
Feedforward
IFETCH
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Pipeline and Execution Timing
MEM WB
DEC / EA MEM
EXECUTE WB
DECODE EA Calc
Figure 6-9
WB
MEM WB
shows basic pipeline flow
6-9