Freescale Semiconductor e200z3 Reference Manual page 302

External Core Complex Interfaces
7.5.1.3 Basic Write Transfer Cycles
During a write transfer, the core provides write data to a memory or peripheral device.
functional timing for basic write transfers. Clock-by-clock descriptions of activity in
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-5. Basic Write Transfers—Single-Cycle Writes, Full Pipelining
• Clock 1 (C1)—The first write transfer starts in clock cycle 1. During C1, the core places valid
values on the address bus and transfer attributes. The burst type (p_[d,i]_hburst[2:0]), protection
control (p_[d,i]_hprot[5:0]), and transfer type (p_[d,i]_htrans[1:0]) attributes identify the specific
access type. The transfer size attributes (p_[d,i]_hsize[1:0]) indicate the size of the transfer. The
byte strobes (p_[d,i]_hbstrb[7:0]) are driven to indicate active byte lanes. The write
(p_[d,i]_hwrite) signal is driven high for a write cycle.
The core asserts transfer request (p_[d,i]_htrans= NONSEQ) during C1 to indicate that a transfer
is being requested. Because the bus is idle, (0 transfers outstanding), the first read request to addr
is considered taken at the end of C1. The default slave drives a ready/OKAY response for the
current idle cycle.
• Clock 2 (C2)—During C2, the write data for the access is driven and the addr
occurs using the address and attribute values (driven during C1) to enable writing of one or more
bytes of memory. The slave device responds by asserting p_[d,i]_hready to indicate the cycle is
completing and drives an OKAY response.
Another write transfer request is made during C2 to addr
because the access to addr
• Clock 3 (C3)—During C3, write data for addr
using the address and attribute values (driven during C2) to enable writing of one or more bytes of
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1 2
nonseq nonseq
addr x addr y
single single
data x
okay
is completing, it is considered taken at the end of C2.
x
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq
addr z
single
data y
okay okay
(p_[d,i]_htrans = NONSEQ), and
y
is driven, and the addr
y
Figure 7-5 shows
Figure 7-5 follow.
4 5
idle
data z
okay
memory access
x
memory access takes place
y
Freescale Semiconductor
x